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| ADM6926 26 port 10/100 mbps ethernet switch controller version 1.0 admtek . com.tw inform atio n in th is d o c u m en t is p r ov id ed in co n n ection w ith ad mtek pr odu cts. ad mtek m a y mak e ch ang e s to sp ecificatio n s an d produ ct d e scri p tio ns at an y time, with ou t no tice. design ers m u st n o t rely on the abse nce or characteristic s of a n y feat ure s or i n st r u ct i o ns m a rked ? r e s erve d? or ? u n d efi n ed? . a d m t e k reserv es th ese fo r fu ture defin itio n an d sh all h a v e n o respon sib i l ity wh atso ev er for con f licts o r in co m p atib ilit i e s arising fro m fu tu re ch ang e s to th em the p r od uct s m a y cont ai n d e si gn defect s o r e r r o rs k n o w as e rrat a , whi c h m a y cause t h e p r od uct t o de vi at e fr om publ i s he d speci fi cat i o n s . c u r r e n t cha r acterized e rra ta are availabl e o n requ est. to ob tain latest doc um ent a t i on pl ease c o nt act y ou l o cal a d m t e k sal e s of fi ce o r vi si t ad m t ek?s we bsi t e at h ttp ://www.admtek . co m . tw *t hi rd - p art y b r an ds a n d nam e s are t h e pr o p e rt y of t h ei r res p ect i v e ow ne rs .
admtek inc. v1.0 about this manual general release intended audience admtek?s custom ers structure this data sheet contains 5 chapters chapter 1 product overview chapter 2 interface descrip tion chapter 3 function description chapter 4. electrical specification chapter 5. packaging revision history d a t e v e r s i o n c h a n g e 08 a u g 20 0 3 1.0 1. first release of ADM6926 customer support admtek incorporated, 2f, no.2, li-hsin rd., science-based industrial park, hsinchu, 300, taiwan, r.o.c. sales information tel + 886-3-5788879 fax + 886-3-5788871 admtek inc. v1.0 table of contents chapter 1 product overview ........................................................................................ 1-1 1 . 1 o v e r v i e w .......................................................................................................... 1 - 1 1 . 2 f e a t u r e s ............................................................................................................ 1 - 1 1 . 3 b l o c k diagram ................................................................................................. 1 - 2 1 . 4 abbreviations ................................................................................................... 1-3 1 . 5 c o n v e n t i o n s ..................................................................................................... 1 - 4 1.5.1 data lengths ............................................................................................ 1-4 1.5.2 register type descriptions ...................................................................... 1-4 1.5.3 pin type descriptions .............................................................................. 1-4 chapter 2 interface description ................................................................................... 2-1 2.1 pin diagram ? adm 6926 (ss-smii interface) ..................................................... 2-1 2 . 2 p i n d e s c r i p t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2 2.2.1 ss-smii networking interface, 60 pins ................................................... 2-2 2.2.2 mii/rmii interface, 28pins ...................................................................... 2-3 2.2.3 p o w e r / g r o u n d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.4 miscellaneous pins, 16 pins ..................................................................... 2-5 chapter 3 function description ................................................................................... 3-1 3.1.1 basic operation ....................................................................................... 3-1 3.1.2 address learning ..................................................................................... 3-1 3.1.3 address aging .......................................................................................... 3-2 3.1.4 address recognition and packet forwarding ......................................... 3-3 3.1.5 trunking port forwarding ...................................................................... 3-4 3.1.6 illegal frames .......................................................................................... 3-4 3.1.7 back off algorithm ................................................................................... 3-4 3.1.8 buffers and queues .................................................................................. 3-4 3.1.9 half duplex flow control ....................................................................... 3-5 3.1.10 full duplex flow control ........................................................................ 3-5 3.1.11 inter-packet gap (ipg) ........................................................................... 3-5 3.1.13 priority control ....................................................................................... 3-6 3.1.14 a l e r t l e d d i s p l a y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.15 broadcast s t orm filter ............................................................................ 3-7 3.1.16 collision le d display ............................................................................. 3-7 3.1.17 bandwidth control ................................................................................... 3-8 3.1.18 smart discard .......................................................................................... 3-8 3.1.19 security support ....................................................................................... 3-8 3.1.20 smart counter support ............................................................................ 3-8 3.1.21 length 1536 mode ................................................................................... 3-8 3.1.22 p h y m a n a g e m e n t ( m d c / m d i o i n t e r f a c e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.1.23 forward special packets to the cp u port .............................................. 3-9 3.1.24 special tag ........................................................................................... 3-10 3.1.25 port 24 and port 25 interface (onl y s s - s m i i p a c k a g e s u p p o r t ) . . . . . . . . . . . 3-12 3.1.26 hardware, eeprom a nd smi interface for configuration .................. 3-13 3 . 2 e e p r o m register format ............................................................................ 3 - 1 7 3.2.1 signature (index: 0h) ............................................................................. 3-20 ADM6926 i 3.2.2 g l o b a l c o n f i g u r a t i o n r e g i s t e r ( i n d e x : 1 h ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 admtek inc. v1.0 3.2.3 port configuration registers (index: 2h ~ 1bh) .................................... 3-21 3.2.4 miscellaneous configuration (index: 1ch) ............................................ 3-23 3.2.5 vlan(tos) priority map (index: 1dh) ................................................. 3-23 3.2.6 forwarding group outbound port map low ....................................... 3-24 3.2.7 forwarding group outbound port map high ...................................... 3-25 3.2.8 p0 vid and pvid shift (index: 5eh) ..................................................... 3-25 3.2.9 p1~p25 vid configuration ................................................................... 3-26 3.2.10 p0, p1, p2, p3 bandwidth control r e gister (index: 78h) ..................... 3-26 3.2.11 p4, p5, p6, p7 bandwidth control r e gister (index: 79h) ..................... 3-27 3.2.12 p8, p9, p10, p11 bandwidth cont rol register (index: 7ah) ................. 3-27 3.2.13 p12, p13, p14, p15 bandwidth cont rol register (index: 7bh) ............. 3-28 3.2.14 p16, p17, p18, p19 bandwidth contro l register (index: 7ch) ............. 3-28 3.2.15 p20, p21, p22, p23 bandwidth cont rol register (index: 7dh) ............. 3-29 3.2.16 p24, p25 bandwidth control register (index: 7eh) .............................. 3-29 3.2.17 bandwidth control enable regi ster low (index: 7fh) .......................... 3-30 3.2.18 bandwidth control enable regi ster high (index: 80h) ........................ 3-30 3.2.19 reserved registers (index: 81h~8ah) .................................................... 3-30 3.2.20 customized phy control g r o u p 0 ( i n d e x : 8 b h ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.2.21 customized phy control group 1 (index: 8ch) .................................... 3-31 3.2.22 customized phy control g r o u p 2 ( i n d e x : 8 d h ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.2.23 customized phy control group 3 (index: 8eh) .................................... 3-32 3.2.24 group 0 phy customized data 0 (index: 8fh) .................................... 3-32 3.2.25 group 0 phy customized data 1 (index: 90h) ................................... 3-32 3.2.26 group 1 phy customized data 0 (index: 91h) ................................... 3-33 3.2.27 group 1 phy customized data 1 (index: 92h) ................................... 3-33 3.2.28 group 2 phy customized data 0 (index: 93h) ................................... 3-33 3.2.29 group 2 phy customized data 1 (index: 94h) ................................... 3-33 3.2.30 group 3 phy customized data 0 (index: 95h) ................................... 3-33 3.2.31 group 3 phy customized data 1 (index: 96h) ................................... 3-33 3.2.32 phy customized enable register (index: 97h) ..................................... 3-33 3.2.33 pppoe con t rol register0 (index: 98h ) ................................................ 3-34 3.2.34 pppoe con t rol register 1 (index: 99h ) ............................................... 3-34 3.2.35 phy control register 0 (index: 9ah) .................................................... 3-35 3.2.36 phy control register 1 (index: 9bh) .................................................... 3-35 3.2.37 disable md io active register 0 (index: 9ch) ....................................... 3-36 3.2.38 disable md io active register 1 (index: 9dh) ...................................... 3-36 3.2.39 port disable register 0 (index: 9eh) ..................................................... 3-37 3.2.40 port disable register 1 (index: 9fh) ...................................................... 3-37 3.2.41 igmp snooping control register 0 (index: a0h) .................................. 3-37 3.2.42 igmp snooping control register 1 (index: a1h) .................................. 3-38 3.2.43 cpu control register (index: a2h) ....................................................... 3-38 3.2.44 special mac forward control register 0 (index: a3h) ....................... 3-39 3.2.45 special mac forward control register 2 (index: a4h) ....................... 3-40 3.2.46 special mac forward control register 2 (index: a5h) ....................... 3-40 3.2.47 trunking enable register 0 (index: a6h) .............................................. 3-41 ADM6926 ii 3.2.48 trunking enable register 1 (index: a7h) .............................................. 3-41 admtek inc. v1.0 3 . 3 switch register map ...................................................................................... 3-42 3.3.1 version id (offset: 0h) .......................................................................... 3-42 3.3.2 link status ( o ffset: 1h) .......................................................................... 3-42 3.3.3 speed status (offset: 2h) ........................................................................ 3-43 3.3.4 duplex status (offset: 3h) ...................................................................... 3-44 3.3.5 f l o w c o n t r o l s t a t u s ( o f f s e t : 4 h ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 3.3.6 address table control and status register ........................................... 3-45 3.3.7 phy control register (offset: bh) ......................................................... 3-51 3.3.8 hardware status (offset: dh) ................................................................. 3-51 3.3.9 receive packet count overflow (offset: eh) ......................................... 3-52 3.3.10 receive packet length c ount overflo w (offset: fh ) .............................. 3-53 3.3.11 transmit packet count overflow (offset: 10h) ..................................... 3-53 3.3.12 transmit packet length count o verflow (offset: 11h) ......................... 3-54 3.3.13 error count overflow (offset: 12h) ...................................................... 3-54 3.3.14 collision co unt overflo w (offset: 1 3 h) ................................................. 3-55 3.3.15 renew counter register (offset: 14h) ................................................... 3-56 3.3.16 read counter control & status register .............................................. 3-57 3.3.17 reload mdio register (offset: 17h) ..................................................... 3-57 3.3.18 spanning tree port state 0 (offset: 18h) .............................................. 3-58 3.3.19 spanning tree port state 1 (offset: 19h) .............................................. 3-58 3.3.20 source port register (offset: 1ah) ........................................................ 3-59 3.3.21 transmit port register (offset: 1bh) ..................................................... 3-59 3.3.22 counter register: offset hex. 0100h ~ 019b ......................................... 3-59 chapter 4 electrical s p ecification ................................................................................ 4-1 4 . 1 d c c h a r a c t e r i z a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 absolute maximum rating ....................................................................... 4-1 4.1.2 recommended operatin g condition s ...................................................... 4-1 4.1.3 dc electrical characteristic s for 3.3v operation .................................. 4-1 4 . 2 a c c h a r a c t e r i z a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1 xi/osci (cr y stal/oscillator) timing ....................................................... 4-2 4.2.1 p o w e r o n r e s e t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.2 eeprom interface timing ...................................................................... 4-3 4.2.3 10base-tx mii outpu t timing ................................................................ 4-3 4.2.4 10base-tx mii input timing ................................................................... 4-4 4.2.5 100base-tx mii outpu t timing .............................................................. 4-5 4.2.6 100base-tx mii input t i ming ................................................................. 4-5 4.2.7 reduced mii timing ................................................................................ 4-6 4.2.8 ss_smii tr ansmit timing ........................................................................ 4-7 4.2.9 ss_smii receive timin g .......................................................................... 4-7 4.2.10 serial management interfa ce (mdc/mdio) timing .............................. 4-8 ADM6926 iii c h a p t e r 5 p a c k a g i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 admtek inc. v1.0 list of figures figure 1-1 ADM6926 block diagram ............................................................................. 1-2 figure 2-1 ADM6926 pin diagram ................................................................................. 2-1 figure 3-1 t h e search p o inter ....................................................................................... 3-48 figure 3-2 address table mapping t o o u t p u t p o r t m a p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 figure 4-1 c r ystal/oscillator tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 figure 4-2 p o wer on reset tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 figure 4-3 e e prom interface tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 figure 4-4 10base-tx m ii output tim i ng ..................................................................... 4-3 figure 4-5 10base-tx mii input tim i ng ........................................................................ 4-4 figure 4-6 100base-tx m ii output tim i ng ................................................................... 4-5 figure 4-7 100base-tx mii input tim i ng ...................................................................... 4-5 figure 4-8 r e duced mii tim i ng (1 of 2) ......................................................................... 4-6 figure 4-9 r e duced mii tim i ng (2 of 2) ......................................................................... 4-6 figure 4-10 ss_smii transm it ti m i ng ........................................................................... 4-7 figure 4-11 ss_smii receive tim i ng ............................................................................ 4-7 figure 4-12 serial managem e nt in terface (mdc/mdio) timing .................................. 4-8 list of table table 4-4-1 electrical abso lute maxim u m rating .......................................................... 4-1 table 4-4-2 recomm ended operatin g condition s .......................................................... 4-1 table 4-4-3 dc electrical charac t e r i s t i c s f o r 3 . 3 v o p e r a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 table 4-4 crystal/osci llator tim i ng ................................................................................ 4-2 table 4-5 p o wer on reset tim ing ...................................................................................... 4-3 table 4-6 e e prom interface tim i ng ............................................................................. 4-3 table 4-7 10base-tx mii output tim i ng ....................................................................... 4-4 table 4-8 10base-tx mii input tim i ng ......................................................................... 4-4 table 4-9 100base-tx m ii output tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-10 100base-tx mii input tim i ng ..................................................................... 4-6 table 4-11 reduced mii tim i ng ..................................................................................... 4-6 table 4-12 ss_smii transm it ti m i ng ............................................................................ 4-7 table 4-13 ss_smii receive tim i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 ADM6926 iv table 4-14 serial managem e nt in terface (mdc/mdio) timing ................................... 4-8 ADM6926 product review chapter 1 pr oduct overview 1.1 overview the ADM6926 is a high perform a nce/low cost , twenty six-port 10/100 mbps ethernet switch controller with all ports supporting 10/100 mbps full duplex switch function. the ADM6926 is intended for applications to standalone-bridge for the low cost ether- switch m a rket. ADM6926 can be programm e d t r unking port active. the trunking port can be connected to server or stacking two switch boxes to enhance the perform a nce. the ADM6926 also supports back-pressure in half duplex m o de and 802.3x flow control in full duplex m ode. w h en back-pressure is enabled, and there is no receive buffer availab l e for the incom i ng packet, th e ADM6926 will force a jam pattern on the receiv i ng po rt in half duplex m ode a nd tr ansm it the 802.3x packet back to receiv i ng end in full duplex m ode. an intelligent address re cognition algorithm m a kes ADM6926 to recognize up to 4096 dif f e rent m a c addresse s and enable s f ilter i ng an d f o rwarding at f u ll wir e speed. the ADM6926 has em bedded sram for the proprietary buffer m a nage m e nt. the sram is us ed to store the inco m i ng/outgoing packets. these buffers pro v ide elastic storag e for transferring data between low- speed and high-speed segm ents and buffer s are efficiently allocated to im prove the efficiency. 1.2 features ? ? ? ? ? ? ? ? ? ? ? ? ? ? admtek inc. 1-1 ? ADM6926 product review x rate-lim it control (64k/128k/256k/512k /1m/4m/10m/20m) x per port auto learning enable/d isable and if disable, fo rward non-learned packet to cpu x mac address table accessible (in each entry, res e rve one bit for cpu to enable/d isab le aging ou t) x forward special m u lticas t, bpdu, gmrp, gvrp and igmp packets to cpu port x 128 pin qfp package with 3.3v/1.8v power supply 1.3 block diagram f i g u r e 1-1 a d m692 6 blo ck diag ram admtek inc. 1-2 cl o c k ge n e r a t o r 10 /100m ma c ee pr om co n t r o l & o r f n / ( ' , q w h u i d f h 10/100 m ma c 10 /100m ma c 10/100m ma c s w it c h in g f a bric e m bed ded mem o r y 0 , , 5 0 , , , q w h u i d f h me m o r y bi s t 10/100m ma c phy co n t r o l i n t e r f ac e co n v er t o r bi a s & , q w h u i d f h 0 ' & 0 ' , 2 6 6 6 0 , , , q w h u i d f h ADM6926 product review 1.4 abbreviations bpdu bridge protocol data u n it crc cyclic redundancy check crsdv carrier sense and data valid da destination address dupcol duplex and collis ion edi eeprom da ta input edo eeprom da ta output eecs eeprom chip select eesk eeprom serial clock esd end of stream delim iter fcs fram e check sequence fet field effect transis t or garp generic attribute registration protocol gmrp garp multicast registration protocol gvrp garp vlan registration protocol igmp internet group managem e nt protocol ipg inter-packe t gap mac media access controller mdc managem e nt data clock mdio managem e nt data input/output mii media ind e p e ndent in terface phy physical layer pll phase lock loop pppoe point to point protocol over ethernet pvid port vlan id qfp quad flat pack qos quality of servic e rmii reduced media indep e n d ent in terface sa source address ss-smii source synchronous serial mii ta turn around tos type of service ttl transistor transistor logic unique universal queue m a nag e m e nt vid vlan id vih voltage input high vil voltage input low admtek inc. 1-3 vlan virtual lan ADM6926 product review 1.5 conventions 1.5.1 data lengths qword 64-bits dword 32-bits word 16-bits byte 8 bits nibble 4 bits 1.5.2 register type descriptions register typ e description ro read only r/ w read and write capable sc self -clea r in g ll latching low, unlatch on read lh latching high, unlatch on read cor clear on read 1.5.3 pin type descriptions pin type description i: input o: output i/o: bi-dire c tion a l od: open drain sche: schm itt trig ger pu: pull up admtek inc. 1-4 pd: pull down ADM6926 interf ace description chapter 2 interface description 2.1 pin diagram ? ADM6926 (ss-smii interface) f i g u r e 2-1 a d m692 6 pin diag ram admtek inc. 2-1 ADM6926 srxd2[ 7 ] vcci k gndi k m0 cr s m0 col m 0 t xd[ 3 ] m 0 t xd[ 2 ] m 0 t xd[ 1 ] m 0 t xd[ 0 ] m0 t x e n m0 t x c l k m0 rxcl k m0 rxd v vcc3o gndo m0 rxd [ 0 ] m0 rxd [ 1 ] m0 rxd [ 2 ] m0 rxd [ 3 ] m1 cr s m1 col m 1 t xd[ 3 ] m 1 t xd[ 2 ] m 1 t xd[ 1 ] m 1 t xd[ 0 ] vcci k gndi k m1 t x e n m1 t x c l k m1 rxcl k m1 rxd v m1 rxd [ 0 ] m1 rxd [ 1 ] m1 rxd [ 2 ] m1 rxd [ 3 ] eesk ed i ed o g ndo srxd0[ 7 ] s t x d 1[ 0] srxd1[ 0 ] c ko50m s t x d 1[ 1] c ko25m srxd1[ 1 ] s t x d 1[ 2] srxd1[ 2 ] vccrg g ndrg vre f c ont ro l vccp l l g ndpl l sync_t x1 s t x d 1[ 3] md c md i o test2 xi xo test1 sync_r x1 srxd1[ 3 ] cl k _ t x 1 vcc3 o g ndo s t x d 1[ 4] cl k _ r x 1 srxd1[ 4 ] s t x d 1[ 5] vcci k g ndi k srxd1[ 5 ] s t x d 1[ 6] srxd1[ 6 ] st xd 2[ 7] s r xd 2[ 6] st xd 2[ 6] s r xd 2[ 5] st xd 2[ 5] re se t l s r xd 2[ 4] cl k _ rx 2 st xd 2[ 4] cl k _ t x 2 s r xd 2[ 3] syn c _r x2 gn do vcc3 o gn di k vcci k st xd 2[ 3] sy nc_ t x2 s r xd 2[ 2] st xd 2[ 2] s r xd 2[ 1] st xd 2[ 1] s r xd 2[ 0] st xd 2[ 0] s r xd 1[ 7] st xd 1[ 7] al e r t stx d 0[0 ] eec s sr xd0 [ 0 ] stx d 0[1 ] sr xd0 [ 1 ] stx d 0[2 ] vc c3o gn do sr xd0 [ 2 ] sy nc_ t x0 stx d 0[3 ] sy nc_ r x0 sr xd0 [ 3 ] cl k _ t x 0 stx d 0[4 ] cl k _ rx0 sr xd0 [ 4 ] vc ci k gn di k stx d 0[5 ] sr xd0 [ 5 ] stx d 0[6 ] sr xd0 [ 6 ] stx d 0[7 ] vc c3o 34 33 32 31 24 23 22 21 15 17 18 19 20 35 36 37 38 14 13 16 25 26 27 28 29 30 2 1 6 4 5 3 7 8 9 10 11 12 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 71 72 73 74 75 70 69 68 67 66 65 99 98 97 96 95 94 93 92 91 10 2 10 1 10 0 126 112 113 114 115 116 117 118 119 120 121 122 123 124 125 111 110 109 108 107 106 105 104 103 127 128 39 40 41 42 43 44 45 46 47 48 49 51 52 53 64 63 62 61 60 59 58 57 56 5 5 54 50 ADM6926 interf ace description 2.2 pin descrip t ion ADM6926 pins are categorized into one of the following groups: ? section 2.2. 1 ss-smii networking in terface, 60 pins ? section 2.2. 2 mii/rmii interface, 28 pins ? section 2.2.3 power/ground ? section 2.2.4 miscellaneous pins, 16 pins 2.2.1 ss-smii netw orking interface, 60 pins admtek inc. 2-2 n a m e t y p e p i n # des c r i p t i o n s r x d 0 [ 0 : 7 ] i , ttl 106,108, 112,116, 120,124, 126,2 port 0 to po rt 7 ss-smi i receive d a ta bit. the receiv e data should be synchronous to th e rising edge of clk_rx0. sync_ r x0 i , ttl 115 port 0 to port 7 ss-smii synchronous signal. this signal is synchronous to the rising e dge of clk_rx0. active high indicates the byte boundary. c l k _ r x 0 i , ttl 119 reference receive clo c k fo r port 0 to port 7. this signal is 125mhz input for ss-smii interface. stxd0 [ 0 : 7 ] o , ttl 8m a 104,107, 109,114, 118,123, 125,127 port 0 to port 7 ss-smii transmit data bit. the transm it data is synchronous to th e rising edge of clk_tx0. sync_ t x0 o , ttl 8m a 113 port 0 to port 7 ss-smii synchronous signal. this signal is synchronous to the rising edge of clk_tx0. act i ve high indicates the byte boundary. c l k _ t x 0 o , t t l 16m a 117 reference transmit c l ock for port 0 to port 7 . this signal is 125mhz output for ss-smii in terface. s r x d 1 [ 0 : 7 ] i , ttl 4,8,10,26, 32,36,38, 40 port 8 to po rt 15 ss-smii receiv e data bit. the receiv e data should be synchronous to the rising edge of clk_rx1. sync_ r x1 i , ttl 25 port 8 to port 15 ss-smii synchronous signal. this signal is synchronous to the rising edge of clk_rx1. active high indicates the byte boundary. c l k _ r x 1 i , ttl 31 reference receive clo c k fo r port 8 to port 15 . this signal is 125mhz input for ss-smii interface. stxd1 [ 0 : 7 ] o , ttl 8m a 3,6,9,18, 30,33,37, 39 port 8 to port 15 ss-smii transmit data bit. the tran s m it data is synchronous to th e rising edge of clk_tx1. sync_ t x1 o , ttl 8m a 17 port 8 to port 15 ss-smii synchronous signal. this signal is synchronous to the rising edge of clk_tx1. active high indicates the byte boundary. c l k _ t x 1 o , t t l 2 7 reference transmit c l ock for port 8 to port 1 5 . this ADM6926 interf ace description n a m e t y p e p i n # des c r i p t i o n 16m a signal is 125 mhz output for ss-smii interface. s r x d 2 [ 0 : 7 ] i , ttl 42,44,46, 54,58,61, 63,65 port 16 to p o rt 23 ss-smii receiv e data bit. the receiv e data should be synchronous to the rising edge of clk_rx2. sync_ r x2 i , ttl 53 port 16 to p o rt 23 ss-smii synchronous signal. this signal is synchronous to the ri sing edge of clk_rx2. active high indicates the byte boundary. c l k _ r x 2 i , ttl 57 reference receive clo c k fo r port 16 to port 2 3 . this signal is 125mhz input for ss-smii interface. stxd2 [ 0 : 7 ] o , ttl 8m a 41,43,45, 48,56,60, 62,64 port 16 to p o rt 23 ss-smii transmit data bit. the transm it data is synchronous to the rising edge of clk_tx2. sync_ t x2 o , ttl 8m a 47 port 16 to p o rt 23 ss-smii synchronous signal. this signal is synchronous to the ri sing edge of clk_tx2. active high indicates the byte boundary. c l k _ t x 2 o , t t l 16m a 55 reference transmit c l ock for port 16 to port 23. this signal is 125 mhz output for ss-smii interface. 2.2.2 mii/rmii interface, 28pins admtek inc. 2-3 n a m e t y p e p i n # des c r i p t i o n m 0 c r s i , ttl pd 68 mii port0 carrier sen s e this pin is internal pull_down. m 0 c o l i , ttl pd 69 mii port0 collision input this pin is internal pull_down. m0txd [0: 3 ] i/o, ttl 8m a pd 73,72,71, 70 mii port 0 transmit d a ta bit[0:3]. synchronous to the rising edge of m0txclk. rmii port 0 transmit data bit[0:1]. synchronous to the rising edge of m0rxclk. rmiimode[1] : value on m0txd[ 3] will be latched a t the rising edge of resetl to c onfigure port 25 as r m ii m ode. rmiimode[0] : value on m0txd[ 2] will be latched a t the rising edge of resetl to c onfigure port 24 as r m ii m ode. m 0 t x e n i / o , ttl 8m a pd 74 mii/rmii port 0 transmit enable. agdis. value on this p i n will be latched at th e r i sing edge of resetl to set aging disable. m 0 t x c l k i , ttl pd 75 mii port 0 transmit clock input. this pin is 2 5 mhz input for mii in terface. m0rxcl k i , ttl pd 76 mii/rmii port 0 receive clock input. this pin is 2 5 mhz input for mii in terface and 50mhz refclk input for rmii interface. ADM6926 interf ace description n a m e t y p e p i n # des c r i p t i o n admtek inc. 2-4 m 0 r x d v i , ttl pd 77 mii port 0 receive data valid. rmii port 0 carrier s e nse/receiv e data valid. this pin is internal pull_down. m0rxd [0: 3 ] i, ttl pd 80,81,82, 83 mii port 0 receive data bit[0:3 ]. rmii port 0 receive data bit[0 :1]. if in rmii mode, m0rxd[3] used for ext_dup_enable and m0rxd[2] used for ext_dup_fu ll. internal pull_down. see sec3.1.27 for details. m 1 c r s i , ttl pd 84 mii port 1 carrier sen s e this pin is internal pull_down. m 1 c o l i , ttl pd 85 mii port 1 collision input this pin is internal pull_down. m1txd [0: 3 ] i/o, ttl 8m a 89,88,87, 86 mii port 1 t ransmit d a ta bit[0 :3]. synchronous to the rising edge of m1txclk. rmii port 1transmit data bit[0:1]. synchronous to the rising edge of m1rxclk. bpen. value on m1txd[ 3] will be latch e d at the rising edge of resetl to set bac k_pressure enable. internal pull_up. fcen. value on m1txd[ 2] will be latch e d at the rising edge of resetl to set flow control enable. internal pull_up. tnken. value on m1txd[ 1] will be latched at the rising edge of resetl to set trunking enable. internal pull_up. ipglving. value on m1txd[ 0] will be latch e d at the rising edge of resetl to se t shorter ipg. internal pull_down. m 1 t x e n o , t t l 8m a pu 92 mii port 1 transmit e n able. ane n. value on this p i n will be latched at th e r i sing edge o f resetl to set auto_negotiation enable. internal pull_up. m 1 t x c l k i , ttl pd 93 mii port1 transmit clock input. this signal is 25mhz input for mii interface. m1rxcl k i , ttl pd 94 mii1 receive clock in put. this signal is 25mhz input for mii in terface and 50mhz refclk input for rmii in terface. m 1 r x d v i , ttl pd 95 mii/rmii port 1 receive data valid. this pin is internal pull_down. m1rxd [0: 3 ] i, ttl pd 96,97,98, 99 mii port 1 receive data bit[0:3 ]. rmii port 1 receive data bit[0 :1]. if in rmii mode, m1rxd[3] used for ext_dup_enable and m1rxd[2] used for ext_dup_fu ll. internal pull_down. see sec3.1.27 for details. ADM6926 interf ace description 2.2.3 po w er/ground pin name pin t y pe pin # pin descrip tion g n d r g a n a l o g ground 12 ground for regulator vcc r g a n a l o g power 11 3.3v po w e r supply for regulator gndp l l a n a l o g ground 16 ground for pll vccp l l a n a l o g power 15 1.8v po w e r supply pll g n d i k d i g i t a l ground 35,50,67, 91,122 ground for core logic v c c i k d i g i t a l power 34,49,66, 90,121 1.8v po w e r supply for core logic g n d o d i g i t a l ground 1,29,52, 79,111 ground for i/o pad vcc3 o d i g i t a l power 28,51,78, 110,128 3.3v po w e r supply for i/o pad 2.2.4 miscellaneous pins, 16 pins admtek inc. 2-5 pin name pin t y pe pin # pin descrip tion ck25mo o, ttl 16m a 7 25mhz clock output. t h is pin will drive out 25mhz. ck50mo/ col_led_ 10m o, ttl 16m a 5 50mhz clock output. t h is pin will drive out 50mhz. col_led_10m. this pin shows c o llis ion led f o r 10m dom a in (see eeprom re gister 1ch, bit[9]) x i i , analog 22 crystal or osc 50mhz input. this is the clock source of pll. the pll will gen e rate 125 mh z f o r ss-smii and 50mhz for rmii and 2 5 mhz for mii. x o o , analog 23 crystal 50mhz output. r e s e t l i , t t l sche 59 reset signal. an active low signal with m i ni mum 100m s duration is required. alert/ col_led_ 100m o, ttl 8m a 103 alert led display. this pin will sh ow the statu s of power- on-diagnostic and broadcast traffic. col_led_100m. this pin shows collision le d for 100m dom a in (see eeprom re gister 1ch, bit[9]) test[2:1 ] i , ttl pd 21,24 industrial test pins. these pins are internal pull_down. m d c o , t t l 16m a 19 management data clock. this pin output 2.2mhz clock to d r iv e phy and access corres p ondin g s p eed an d du p lex and link status throu g h ADM6926 interf ace description pin name pin t y pe pin # pin descrip tion mdio. m d i o i / o , ttl 8m a pu 20 management data. this pin is in-out to ph y. w h en resetl is low, this pin will be tri-state. this pi n is internal pull_up. e e s k i / o , ttl 4m a pu 100 eeprom serial clock. this pin is clock source for eeprom. w h en resetl is low, it will be tri- state. th is p i n is in tern al pull-up. e e c s i / o , ttl 4m a pd 105 eeprom chip select. this pin is chip enable for eeprom. w h en resetl is low, it will be tri-s t ate. this pin is interna l pull-down. e d i i / o , ttl 4m a pu 101 eeprom serial data input. this pin is output for serial data transfer. w h en resetl is low, it will be tri-state. t h is pin is internal pull-up. e d o i , ttl pu 102 eeprom serial data output. this pin is input for serial data transfer. this pin is internal pull-up. cont rol o , analog 14 fet control signal. the pin is used to control fet for 3.3v to 1.8v regulator. v r e f i , analog 13 regulator control input signal. admtek inc. 2-6 ADM6926 function description chapter 3 function description 3.1 introduction the ADM6926 uses a ?store & forward? swit ching approach for the following reasons: 1) store & forward switch es allow s w itchi ng between different speed m e dia (e.g. 10basex and 100basex). such switches require the large elastic buffers, especially bridging between a server on a 100mbps ne twork and clients on a 10mbps segm ent. 2) store & forward switches im prove overa ll network perform a nce by acting as a ?network cache? 3) store & forward switches prevent the forwarding of corrupted packets by the fra m e check sequence (fcs) before forwarding to the destination port. 3.1.1 basic operation the ADM6926 receiv e s incom i ng p ackets from one of its ports, uses th e source ad dress (sa) and vid to update the address table, an d then forwards the packet to the output ports determ ined by the destina tion address (da) and vid. if the da and vid are not found in the addre ss table, the ADM6926 treats the packet as a broadcast packet and forwards the packet to the other ports within the same group. the ADM6926 autom a tically learns the port num b er of attached netw ork devices by exam ining the sa and vid of all incom i ng pa ckets. if the sa and vid are not found i n the address table, the d e v i ce adds it to the tab l e. 3.1.2 address learning the ADM6926 provides two ways to create the entry in th e address table: dynami c learning and m a nual learning. a four -way ha sh algorithm is im plem e n ted to allow 4 dif f erent addresses to be stored at the sam e location. up to 4k entries can be created and all entries are stored in the intern al s s ram. t w o param e ters, sa and vi d, are com b ined to generate the 10-bit hash key to allow th at the sam e addresses with dif f erent port num b er can exist in the table at the s a m e ti m e . 1. dyna m i c learning the ADM6926 searches for sa and vid of an incom i ng packet in the address table and acts as follo w s: admtek inc. 3-1 if the sa+vid was not found in the addres s table (a new addr ess), the ADM6926 waits until the en d of the packet (non -error pack et) and updates the add r es s table. if the ADM6926 function description sa+vid was found in the address table, th en aging value of each corresponding entry will be r e set to 0. dynam i c lea r ning will be disabl ed in the f o llowin g condition : (1) security violation happened. (2) the packet is a pause fram e . (3) the first bit of sa is 1?b1. (4) the packet is an erro r packet (too long, too short or fcs error). (5) the cpu port leaning function is disabl ed or enabled but the cpu port instructs the switch n o t to le arn th e packet. (6) the port is in the disabled or blocki ng-not-listening state in the spanning tree protocol. 2. manual l earning the ADM6926 im ple m ents the m a nual learning through the cpu?s help. the cpu can create or remove any e n try in the address table. each entry could be static or pointed t o the outpu t p o rt m a p table. ?static? m eans the entry will not be aged forever. it is useful in the security function (forward unknown packets to the cpu por t or discard) or m onitor function (forward m onitored address to the sp ecific port). o u tput port m a p table is also helpf u l in th e igmp f u nction ( i f the num b er of the output port is m o re than one) or the users want to redirect th e special packets with reserved da. 3.1.3 address aging the ADM6926 will periodically (3 00m s ) rem o ve the non-static addres s in the add r es s table. this could help to prevent a s t ation leaves the network and occup i es a table s p ace for a long tim e . aging function can be disabled from the hardware pin. admtek inc. 3-2 ADM6926 function description 3.1.4 address recognition and packet f o rw arding the ADM6926 forwards the incom i ng packets be tween bridge ports according to the da and vid as follows: admtek inc. 3-3 da da+ v i d wa s f o u n d in t h e ad dr ess tab l e (en t r y no t po in t e d to th e ou tpu t po rt m a p tab l e) da+ v i d wa s fo u nd i n t h e ad dress tab l e (en t ry po in ted t o th e out put p o rt m a p t a bl e ) da+ v i d was n o t f o u n d in the address table no secu rity vi o l atio n fo rwa r d pac k et s t o t h e p o rt d e term in ed b y th e ad dress table. the pac k et m a y be d r op ped b e c a u s e o f f o r w a r d i n g g r o u p bo u nda ry vi ol a t i on. forwa r d packets to the port s d e term in ed by th e ou tpu t po rt m a p t a bl e c o n s t r ai ne d by t h e f o r w ard i ng g r ou p. fo rwa r d pac k et s t o t h e o t her p orts with in the sam e fo rward i ng g r ou p. security vio l atio n unicast addre ss d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu no secu rity vi o l atio n fo rwa r di ng pa cket s t o t h e ot her p o rts with i n th e same f o r w ard i ng g r ou p. forwa r d packets to the port s d e term in ed by th e ou tpu t po rt m a p t a bl e c o n s t r ai ne d by t h e f o r w ard i ng g r ou p. fo rwa r d pac k et s t o t h e o t her p orts with in the sam e fo rward i ng g r ou p. security vio l atio n broa dcast address (al l 1? b1 ) d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu no secu rity vi o l atio n fo rwa r di ng pa cket s t o t h e ot her p o rts with i n th e same f o r w ard i ng g r ou p. forwa r d packets to the port s d e term in ed by th e ou tpu t po rt m a p t a bl e c o n s t r ai ne d by t h e f o r w ard i ng g r ou p. fo rwa r d pac k et s t o t h e o t her p orts with in the sam e fo rward i ng g r ou p. security vio l atio n reserve d address (0 1- 8 0 -c 2- 0 0 - 0 0- x x , with th e op tion to fo rwa r d no rm ally ) sam e as the above sam e as the above sam e as the above no secu rity vi o l atio n forwa r d t h e packet t o t h e cpu po rt . forwa r d the packet to t h e c p u po rt . forwa r d the packet to t h e cpu po rt . security vio l atio n reserve d address (0 1- 8 0 -c 2- 0 0 - 0 0- x x , with th e op tion to fo rwa r d to cp u) sam e as the above sam e as the above sam e as the above no secu rity vi o l atio n discard the pa cket. discard th e pa cket. discard the pa cket. security vio l atio n reserve d address (0 1- 8 0 -c 2- 0 0 - 0 0- x x , with th e op tion to di scar d) sam e as the above sam e as the above sam e as the above no secu rity vi o l atio n forwa r d t h e packet t o t h e cpu po rt . forwa r d the packet to t h e c p u po rt . forwa r d the packet to t h e cpu po rt . security vio l atio n igm p pac k et (po r t en ab le igmp) d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu ADM6926 function description da da+ v i d wa s f o u n d in t h e ad dr ess tab l e (en t r y no t po in t e d to th e ou tpu t po rt m a p tab l e) da+ v i d wa s fo u nd i n t h e ad dress tab l e (en t ry po in ted t o th e out put p o rt m a p t a bl e ) da+ v i d was n o t f o u n d in the address table no secu rity vi o l atio n fo rwa r d pac k et s t o t h e p o rt d e term in ed b y th e ad dress table. the pac k et m a y be d r op ped b e c a u s e o f f o r w a r d i n g g r o u p bo u nda ry vi ol a t i on. forwa r d packets to the port s d e term in ed by th e ou tpu t po rt m a p t a bl e c o n s t r ai ne d by t h e f o r w ard i ng g r ou p. forwa r d pac k ets according the mu lticast op tio n. security vio l atio n igm p pac k et (p ort di sabl e i g m p ) d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu no secu rity vi o l atio n fo rwa r d pac k et s t o t h e p o rt d e term in ed b y th e ad dress table. the pac k et m a y be d r op p ed b e c a u s e o f f o r w a r d i n g g r o u p bo u nda ry vi ol a t i on. forwa r d packets to the port s d e term in ed by th e ou tpu t po rt m a p t a bl e c o n s t r ai ne d by t h e f o r w ard i ng g r ou p. forwa r d pac k ets according the mu lticast op tio n. security vio l atio n othe rs d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu d r op o r fo rw ard to cpu 3.1.5 trunking port forw ar ding ADM6926 supports the trunking forwarding and any port could be assigned to the trunking port. w h en one or m o re of the mem b ers link fail, the ADM6926 will autom a tically change th e transm it path f r om the failed link port to norm a l link port. port based load balancing is imple m e nted to distribute the loading. 3.1.6 illegal frames the ADM6926 will dis card all illegal fram es su ch as runt packet (less than 64 by tes), oversize packet (greater than 1518 or 1522 bytes) or bad crc. 3.1.7 back off algorithm the ADM6926 im ple m ents the truncated exponen tial back off algorith m compliant to the 802.3 standard. ADM6926 will restart the back off algorithm by choosing 0-9 collision count. after 16 consecutive retransm it trials , the ADM6926 resets the collision counter. 3.1.8 buffers and queues admtek inc. 3-4 the ADM6926 incorporates 26 transm it queues and receive buffer area for the 26 ethernet ports. the receive buffers as well as th e tran sm it queues ar e lo cated within the ADM6926 a l ong with the switch fabric. the buffe rs are divided into 640 blocks of 256 ADM6926 function description bytes each. the queues of each po rt are m a naged acco rding to each port?s read/write pointer. input buffers and output queues are m a intain ed through proprietary patent pending unique ( u niversal q u eue m a nagem e nt) schem e . 3.1.9 half duplex flow control back-pressure is supported for half-duplex operation. when the ADM6926 cannot allocate a receive b u ffer for an i n com i ng pa cket (buffer full), the devic e will transm it a jam pattern on the port, thus f o rcing a collision. 3.1.10 full duplex flow control when full duplex port runs out of it s receive bu ffer, a pause command will be issued by ADM6926 to notice the packet sender to pa use transm ission. this fram e based flow control is totally com p liant to ieee 802.3x. wh en flow control hardware pin is set to high during power on reset and p e r port p ause is enab led , ADM6926 will ou tput and accept 802.3 x flow control packet. 3.1.11 inter-packet gap (ipg) ipg is the id le tim e between any two successiv e packets fro m the sam e port. the value is 9.6us for 10mbps ethernet and 960ns for 100mbps fast ethernet. 3. 1. 12 p o rt v l an or t a g vl a n sup po rt admtek inc. 3-5 two vlan settings are supported by the ad m6926: the port-based valn or the tag- based vlan. for the port-based vlan the ADM6926 will use the p o rt num ber as the index to loo kup the forwarding tab l e. for the tag-based vlan, the ADM6926 will us e the vid to lookup the f o rwarding table. each po rt is assigned a port vid as the default vid if tag-based vlan is used. the ADM6926 will check tag, rem ove tag, insert tag, and re-calculate crc if packet is changed: ADM6926 function description (1 ) packets received are un tagged (2) packets received are tag g ed force no tag bypass out put p o rt i s t a gge d or not act i on no no no the ta g i s rem ove d. y e s n o n o tag as th e orig in al. th e priority in t h e tag h e ad er is not ch eck e d and vid will n o t chan ge e v e n i f vi d i s 0 o r 1. no yes no tag as t h e o r igin al. th e priority in th e tag heade r is c h ec ked and if t h e vid is 0 or 1, i t m a y chan ge t o p v i d (se e eepr o m re gi st er 1ch , b i t [ 3] ) n o n o y e s tag as t h e o rigin a l. th e priority in th e tag heade r is c h ec ked and if t h e vid is 0 or 1, i t m a y chan ge t o p v i d (se e eepr o m re gi st er 1ch , b i t [ 3] ) no yes yes tag as t h e o r igin al. th e priority in th e tag heade r is c h ec ked and if t h e vid is 0 or 1, i t m a y chan ge t o p v i d (se e eepr o m re gi st er 1ch , b i t [ 3] ) y e s y e s n o tag as th e o r igin al. th e p r i o ri ty in th e tag h ead er is no t ch eck ed . th e vid will n o t change. y e s n o y e s th e tag will b e ad d e d and p ack et will b e do ub le tagg ed o u t p u t . th e vid will no t change. y e s y e s y e s tag as th e o r igin al. th e p r i o ri ty in th e tag h ead er is no t ch eck ed . th e vid will n o t change. 3.1.13 priority control the ADM6926 provides two priority queues o n each outp u t port. fiv e ways could be used to ass i g n a priority to a packet. (1) the priority assigned to each receiving port. (2) the priority field in the 802.1q tag header. (3) the ipv4 tos field in the ipv4 header. (4 ) priority assigned by the cpu. (5) managem e nt packet (high priority assigned). admtek inc. 3-6 force no tag bypass out put p o rt i s t a gge d or not act i on no no un tag as th e o r ig in al. yes no un tag as th e o r ig in al n o y e s ad d tag . d on? t car e yes yes un tag as th e o r ig in al ADM6926 function description 3.1.14 alert led display two functions are displayed through the alert led. 1. diagnostic mode after pow er on. a) after reset or power up, led keeps on at least 3 second, a nd processes internal ssram self-test. b) if test passes, the ADM6926 turns off led and goes to the broadcast storm m ode. c) if ssram t e st fails, the ADM6926 turns off led, then keeps on. 2. broadcast stor m mo de after ss ram self-t est. pac k ets w i th da = 48?hffffffffffff w ill be counted into the storm coun ter. two thresholds (rising and falling) are used to control the broadcast storm . a) tim e scale: 50m s is used. the m a x packet number in 100b aset is 7490. the m a x packet number in 10baset is 749. b) port rising threshold. b r oa dcast s t or m thre shold. 00 01 10 11 al l 1 0 0 t x di sabl e 10 % 2 0 % 4 0 % not al l 10 0t x di sabl e 1 % 2 % 4 % c) port falling threshold b r oa dcast s t or m thre shold. 00 01 10 11 al l 1 0 0 t x di sabl e 5% 10 % 20 % not al l 10 0t x di sabl e 0. 5% 1% 2% 3.1.15 broadcast storm filter if broadcas t storm i ng f ilter is enab led, the broa dcast p ackets (da = 48 ?hf f f f -ff ff -fff f ) over the ris i ng thresho l d within 50 ms will be d i s carded when the alert le d is turned on. 3.1.16 collision l e d display two collisio n leds are supported. (s ee eeprom register 1ch, bit[9]) 1) 100m collis ion led. if collision happens in one of the ports configured 1 00m, the 100m collis ion led will flash in rate of 2hz. 2) 10m collis ion led. if collis ion hap p ens in one of the ports conf igured 1 0 m, the 10m collis ion led will f l ash in ra te of 2hz. admtek inc. 3-7 ADM6926 function description 3.1.17 bandw i dth control the ADM6926 allows the user to lim it the bandw idth for each input or output port. 64k, 128k, 256k, 512k, 1m, 4m, 10m and 20m are supported. 3.1.18 smart discard the ADM6926 supports a sm art m echanism to discard pack ets early according to their priority to prevent the resource blocked by the lo w priority . t h e discard ratio is as follows: discar d mode utilizatio n 00 01 10 11 0 0 0 % 0 % 0 % 0 % 0 1 0 % 0 % 25 % 50 % 1 1 0 % 25 % 5 0 % 7 5 % 3.1.19 security su pport 4 level security schem e s are supported by the ADM6926. all the security violation address will not be autom a tically learned. the violated packet could be forwarded to the cp u port for managem e nt or discarded. when cpu is not present, adm 6926 also provides a sim p le wa y to lock the first address to preven t illegal address access. 3.1.20 smart counter support six counters per port are supported by the ADM6926. 1) receive packet count. 2) receive packet length count. 3) transm it packet count. 4) transm it packet length count. 5) the error c ount 6) the collisio n count. 3.1.21 length 1536 mode the ADM6926 provides a function to enable th e port to receive packets up to 1536 byte. 3.1.22 phy management (mdc/mdio interface) the ADM6926 uses the mdc/mdio interface to set the ph y status. after the reset or power up, th e mdc/mdio controller will de lay about 130ms to wait for the phy to ready. the ADM6926 supports two ways to configure th e phy setting. 1) phy m a ster. the switch only reads th e phy status (speed, duplex, link, and pause). this m ode is useful when user s want to configure phy through the cpu help. the ADM6926 supports an indirect wa y (a phy cont rol register) for cpu to acces s phys. 2) phy slave. the switch uses the ee prom setting to contro l the phy attached (only speed, duplex, link , and pause are supported). after the port setting changed, the ADM6926 will use the new se tting to program the phy again and update the status. 8 comm ands are provided in this m ode to allow the custom er to custom ize the phy settin g. admtek inc. 3-8 ADM6926 function description note: the phy address attached to port 0 is 5?h8, th e p hy address attached to port 1 is 5?h9,.., the phy address attached to port 23 is 5?h1f , the phy address attached to port 24 is 5?h7 and the phy address attached to port 25 is 5?h8. 3.1.23 forw ard special packets to the cpu port (igmp and spanning tree support) ADM6926 will forward the special packets to th e cpu port to provide th e m a nage m e nt function. 1) da is 01-80-c2-00-00-00 (bpdu) 2) da is 01-80-c2-00-00-02 (slow protocol) 3) da is 01-80-c2-00-00-03 (802.1x pae) 4) da is 01-80-c2-00-00- 04 ~ 01-80-c2-00-00-0f 5) da is 01-80-c2-00-00-20 (gmrp) 6) da is 01-80-c2-00-00-21 (gvrp) 7) da is 01-80-c2-00-00-22 (gvrp) 8) da is 01-00-5e-xx-xx-xx and protocol field is 2 f o r ipv4 (ig mp) admtek inc. 3-9 ADM6926 function description 3.1.24 special tag the ADM6926 has an ability to in sert 4byt e special tag when packets transm itted to the cpu port or to rem o ve 8byte additiona l tag in the packets when p ackets are receiv e d from the cpu port. the co nfigura tion is shown in the cpu configuration register. th is special fu nction allow s th e cpu to know the source port which will b e used in the igmp snooping , spanning tree or the security function. the cpu also could inse rt addition a l 8- byte tag to instruc t the s w itch to han d le the pa ck ets. the packets form at is as follows: 8 7 6 5 4 3 2 1 pr e a m b le sfd sfd de st i nat i on addre s s source addre s s s p e c ia l t a g len gth / t y p e m a c cl i e nt dat a m a c cl i e nt dat a pad fram e ch e c k se que nce 7 o c tets 1 o c tet 6 o c tets 6 o c tets 8 o c tets 2 o c tets 46--1500 o c tets 4 o c tets lab e l o u t p u t p o r t m a p[ 2 6 : 2 0 ] o u t put p o rt m a p[19 : 12] o u t put p o rt m a p[11 : 4 ] re s e r v e d re s e r v e d re s e r v e d pr e a m b le sfd sfd de st i nat i on addre s s source addre s s s p e c ia l t a g len gth / t y p e m a c cl i e nt dat a m a c cl i e nt dat a pad fram e ch e c k se que nce 7 o c tets 1 o c tet 6 o c tets 6 o c tets 4 o c tets 2 o c tets 46--1500 o c tets 4 o c tets lab e l 8 7 6 5 4 3 2 1 s ourc e p o rt [4: 0 ] re s e r v e = 0 ta g [ 7: 0] ta g [ 15: 8] tr a n s m i t en d r ecei ve e n d 8 7 6 5 4 3 2 1 1s t b y t e 2nd b y t e 3r d b y t e 4t h b y t e 1 s t b y te 2n d b y t e 3r d b y t e 4t h b y t e 5t h b y t e 6t h b y t e 7t h b y t e 8t h b y t e o u t p ut p o rt m a p [ 3: 0 ] o u t put p o rt m a p v a l i d q u eue v a l i d q u eue s e l ect l e a r n v a lid lea r n s e l ect admtek inc. 3-10 ADM6926 function description special tag fields configurati on description d e f a u l t label the field is used for cpu to deci de if the special tag is valid. if the switch finds the label doesn?t eq ual to the value assigned by the eeprom, it m u st receiv e as the no rm al mode. this case exis ts when user wants the switch to insert 4 byte sp ecial tag even for pause packets. 8?b0 output port map valid 1 = the switch is ins t ructed to overrid e the switch operation. it will forward the packets following the output port map field. 0 = the switch will trea t the packe t a s the norm a l m ode. 1?b0 output port map[26:0] bit[26] = 1, the cpu wa nts to forwar d packets to more than 2 ports. bit[26] = 0, the cpu wa nts to fo rward packets to only one port. bit[x], x = 0 ~25, the cpu wants to forward packets to port x. exa m ple: 1. the cpu wants to forw ard packet to p1 and p2 then the output port map is as follows: bit 26 25~24 23~16 15~8 7~0 map 1 00 0000_0000 0000_0000 0000_0110 2. the cpu wants to forward packets to p5 only. bit 26 25~24 23~16 15~8 7~0 map 0 00 0000_0000 0000_0000 0010_0000 27?h0 tag[25:0] this value is the sam e as the tag header if the c p u port is c onf igured to a tag port. 16?h0 source port [4: 0 ] this field in dicates the s ource port the packet com e s from . 5?h0 queue valid 1 = the switch is ins t ructed to overrid e the switch operation. it will forward the packets using the queue select field. 0 = the switch will trea t the packe t s as the norm a l m ode. 1?b0 queue select 1 = mapped for high queue 0 = mapped for low queue 1?b0 learn valid 1 = the switch is instructed to ove rride the switch operation. the cpu port will use the learn field to decide how to learn the packet. 0 = the switch will trea t the packe t s as the norm a l m ode. that is, the cpu port will learn or disable learning acc ording the d i sable cpu port learning function configured in the cpu control register. . 1?b0 learn select 1 = learn th e packet. 0 = don?t learn the packet 1?b0 admtek inc. 3-11 ADM6926 function description 3.1.25 port 24 and port 25 interface (only ss-smii package su pport) three interfaces in po rt 24 and port 25 are suppo rted by th e ADM6926: (1) mii in terface (2) rmii interface (3) r e se rved m ii interface. 1. mii interface diagram tx _ c lk tx _ e n t xd[ 0 ] t xd[ 1 ] t xd[ 2 ] t xd[ 3 ] rx _ c l k rx _ d v r xd[ 0 ] r xd[ 1 ] r xd[ 2 ] r xd[ 3 ] crs co l p hy m0 t x c l k m0 t x e n m 0 t xd0 m 0 t xd1 m 0 t xd2 m 0 t xd3 m0 r x c l k m 0 r xdv m 0 r xd0 m 0 r xd1 m 0 r xd2 m 0 r xd3 m0 c r s m0 c o l po r t 2 4 (m ii ) tx _ c lk tx _ e n t xd[ 0 ] t xd[ 1 ] t xd[ 2 ] t xd[ 3 ] rx _ c l k rx _ d v r xd[ 0 ] r xd[ 1 ] r xd[ 2 ] r xd[ 3 ] cr s co l p hy m1 t x c l k m1 t x e n m 1 t xd0 m 1 t xd1 m 1 t xd2 m 1 t xd3 m1 r x c l k m1 r x d v m 1 r xd0 m 1 r xd1 m 1 r xd2 m 1 r xd3 m1 c r s m1 c o l po r t 2 5 (m ii ) 2. rmii interface cl k r ef tx _ e n t xd[ 0 ] t xd[ 1 ] crs _ d v r xd[ 0 ] r xd[ 1 ] ph y m0 r x c l k m0 t x e n m 0 t xd0 m 0 t xd1 m 0 r xdv m 0 r xd0 m 0 r xd1 po r t 2 4 (r m ii) clk r ef tx _ e n t xd[ 0 ] t xd[ 1 ] crs _ d v r xd[ 0 ] r xd[ 1 ] p hy m 1 rx cl k m1 t x e n m 1 t xd0 m 1 t xd1 m 1 r xdv m 1 r xd0 m 1 r xd1 po r t 2 5 (r m i i) 50m h z 50m h z 3. reversed mii interface rx _ c l k rx _ d v rx d[ 0 ] rx d[ 1 ] rx d[ 2 ] rx d[ 3 ] tx_ c l k tx_ e n txd[ 0 ] txd[ 1 ] txd[ 2 ] txd[ 3 ] crs co l cp u (m i i) m0 t x c l k m 0 txen m0 t x d 0 m0 t x d 1 m0 t x d 2 m0 t x d 3 m 0 rxclk m0 r x d v m0 r x d 0 m0 r x d 1 m0 r x d 2 m0 r x d 3 m0 c r s m0 c o l por t 24 (r e v e r s e d m i i ) rx _ c lk rx _ d v rx d [ 0] rx d [ 1] rx d [ 2] rx d [ 3] tx _ c l k tx _ e n tx d [ 0 ] tx d [ 1 ] tx d [ 2 ] tx d [ 3 ] cr s co l cp u (m i i) m1 t x c l k m1 t x e n m1 t x d 0 m1 t x d 1 m1 t x d 2 m1 t x d 3 m 1 rxclk m1 r x d v m1 r x d 0 m1 r x d 1 m1 r x d 2 m1 r x d 3 m1 c r s m1 c o l po r t 25 ( r ev er s e d m i i ) admtek inc. 3-12 ADM6926 function description 3.1.26 hardw a re, eeprom and smi interface for configuration three ways are supported to configure the settin g in the ADM6926: (1) hardware settin g (2) eerprom interface (3) smi interf ace. users could use eeprom and smi interf ace s com b ined with the cpu port to pr ovide proprietary functions. four pins are needed when using these two interfaces. see the following figure as a descrip tion. ad 3110 eep r o m ( 93c66) cp u eec s ees k edi edo 1. hardw a r e setting the ADM6926 provides som e hardware pins wh ere values reside on during power on or reset will be strapped for the default setting. admtek inc. 3-13 ss-smii pin nam e rm ii pi n nam e descri pt i on m1 txd0 m 1 txd0 ipg a v erag e 92 b it ti m e . in tern ally pu lled do wn . 1 = e n ab le ipg a v e r ag e 92 . 0 = disa ble ipg a v era g e 92. m1 txd1 m 1 txd1 t r unk en . in tern ally pu lled up . 1 = t r u n k i ng en ab le. use eeprom to config ure th e trunk me m b er . 0 = t r un ki n g di sabl e. the a d m 6 9 2 6 has n o t r u nki ng f u n c t i on e v en i f e e pr om set s . m1 txd2 m 1 txd2 pau s e. in tern al ly pu lled up. 1 = the swi t c h al l o ws t h e pau s e f unct i o n. t h i s fu nct i o n ca n be di sabl e d by t h e eeprom. 0 = th e switch do esn ? t allow th e pau s e fun c t i o n ev en if eeprom set. the on ly way to start th e pause fu n c tion is th rou g h t h e cpu h e lp . m1 txd3 m 1 txd3 back -pressu r e. in tern ally pu lled up. 1 = the swi t c h al l o ws t h e b a c k - p ress u r e f u n c t i on. thi s f u n c t i on ca n be di sabl ed by the eepr o m. 0 = th e switch do esn ? t allow th e back-press ure f unct i o n e v en i f eepr o m set . m 1 t x e n m 1 t x e n a u t o - neg en . in tern ally pu ll ed up. 1 = th e switch allo ws th e au to -neg o tiatio n fu n c tion . th is fu n c tion can b e d i sab l ed by the eepr o m. 0 = th e switch do esn ? t allow au t o -neg o tiatio n fun c tio n even if eepr o m set. th e o n l y way to start th e au to-neg o tiatio n fun c tio n is throug h th e cpu h e lp. m 0 t x e n m 0 t x e n ag i n g dis. in t e rn ally pu lled down . 0 = th e switch will ag e t h e entry in th e add r ess tab l e.. 1 = th e switch will no t ag e the en try i n th e ad dress tab l e. m0 txd0 d on? t su ppo r t m0 txd2 d on? t su ppo r t po rt 2 4 inte rfa ce co nfig u r ation . m0tx d 0 m 0 tx d2 i n ter f a ce 0 0 p o rt 24 is c o nfi g ur ed to m ii i n s s -sm ii pac k ag e (inter nal valu e. x 1 p o rt 24 is c o nfi g ured to rmi i i n ss- smii pac k a g e. 1 0 p o rt 24 is c o nfi g ured to re verse d mi i i n s s -s mii pac k age . ADM6926 function description ss-smii pin nam e rm ii pi n nam e descri pt i on m0 txd1 d on? t su ppo r t m0 txd3 d on? t su ppo r t po rt 2 5 inte rfa ce co nfig u r ation . m0tx d 1 m 0 tx d3 i n ter f a ce c o nfi g u r ed to m ii i n s s -sm ii pac k ag e (inter nal valu e. x 1 p o rt 25 is c o nfi g ured to rmi i is ss- smii pac k a g e. 1 0 p o rt 25 is c o nfi g ured to re verse d mi i i n s s -s mii pac k age . when port 24 or port 25 is configured to rm ii mode in ss-smii package, we can use the hardware pins to configure dupl ex status of these two ports. por t 24 du p l ex con f igur atio n m 0 rx d 3 m 0 rx d 2 descri p t i o n 0 0 du pl ex st at us i s det e rm i n ed a s p o rt 0 ~ p o rt 23 . 0 1 du pl ex st at us i s det e rm i n ed a s p o rt 0 ~ p o rt 23 . 1 0 fu ll dup l ex is d e term in ed . 1 1 hal f d upl e x i s det e rm i n ed. por t 25 du p l ex con f igur atio n m 1 rx d 3 m 1 rx d 2 descri p t i o n 0 0 du pl ex st at us i s det e rm i n ed a s p o rt 0 ~ p o rt 23 . 0 1 du pl ex st at us i s det e rm i n ed a s p o rt 0 ~ p o rt 23 . 1 0 fu ll dup l ex is d e term in ed . 1 1 hal f d upl e x i s det e rm i n ed. 2. eepro m interfa c e the eeprom interf a ce is p r ovided so the users cou l d easily con f igure the s e tting without cpu?s help. because the eeprom in terface is the sam e as the 93c66, it also allows th e cpu to write the eeprom regis t er and renew the 93c66 at the sam e tim e. after the power up or reset (default value from t h e hardware pins fetched in this stage), the ADM6926 will auto m a tically detect the presence of the eeprom by reading the address 0 in the 96c66. if the value = 16?h4154, it will read all the data in the 93c66. i f not, the ADM6926 will stop loading the 93c66. the user als o could pull down the edo to force the ADM6926 not to load the 93c66. the 93c66 loading tim e is around 30m s . then cpu should give the high-z value in the eecs, eesk and edi pins in this period if we really want to use cp u to read or write the regi sters in the ADM6926. the eeprom interface needs only one w r ite comm and to com p lete a writing operation. if updating the 93c66 at the sam e tim e is necessary, three comm ands w r ite enable, w r ite, and w r ite disable are needed to complete this job (see 93c66 spec. for a reference). users should note that the eerpo m interface only allows the cpu to write the eeprom register in the ADM6926 and doe sn?t support the read c o mm and. if cpu gives the read command, ADM6926 will not respond and 93c66 will respond with the value. users should als o note that one additio nal eesk c y cle is need ed between any continuous comm ands (read or w r i t e). admtek inc. 3-14 ADM6926 function description (1) read 93 c66 via the eeprom i n terface (in d ex = 2, data = 16?h111 1). 1 1 0 a7 a6 a5 a4 a3 a2 a1 a0 0 d1 5 d1 4 d13 d1 2 d11 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 star t o p c o d e eep r om ad res s (in d e x ) du mmy ee cs(cpu ) ees k ( c p u) e d i (cpu ) e d o ( 9 3c 46 ) on e mo re eesk is n eed ed ee pr om r e ad oper a t i o n dat a (2) w r ite eeprom registers in the a d m6926 (index = 2, data =16?h2222). 0 1 0 a7 a6 a5 a4 a3 a2 a1 a0 s t a r t o p c ode eep r o m ad re s s (in d e x ) eec s ( c p u) ee sk(cpu) e d i (cpu ) on e mo re eesk is n e e d ed e e p ro m w r i t e o p er at i o n d1 5 d1 4 d1 3 d1 2 d1 1 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data 3. smi interface the smi consists of two pins, m a nagem e nt data clock (eesk) and m a nagem e nt data input/output (edi). the ADM6926 is designed to support an eesk frequency up to 25 mhz. the edi pin is bi-direc tional and m a y be shared with other devices. eecs pin m a y be needed (p ulled to low) if eeprom interface is also u s ed. the edi pin requires a 1.5 k ? (a) preamble suppression the smi of ADM6926 supports a pream ble suppression m ode. the ADM6926 requires a single initialization sequ ence of 32 bits of pream ble following power-up/hardware reset. this requirem e nt is generally m e t by pullin g - up the resistor o f edi while the ADM6926 will respond to m a nage m e nt accesses without p r eam ble, a m i ni m u m of one idle b it between m a nagem e nt transactions is required. admtek inc. 3-15 ADM6926 function description when ADM6926 detects that th ere is address m a tch, then it will en able read/w rite capability fo r external access. w h en addre ss is mism atched, then ADM6926 will tri-state the edi pin. (b) read sw itch register via smi in terface (offset hex = 10?h2, data = 32?h2600_0000) ee s k edi ( c p u) e d i ( a d 311 0) z 0 1 1 0 0 0 0 0 0 0 0 0 1 0 z 0 0 0 1 0 0 1 1 0 0 0 0 0 0 z pr eam b l e s t a r t op c o de (r e a d ) r e gis t e r a ddr e s s ( 10' h 2 i n t h i s e x a m ple ) t a r e gi s t e r d a t a ( 3 2 ' h 2 6 0 0 000 0 i n t h i s e x a m pl e) ~ ~ s m i re ad o p e r a tio n o n e mo re eesk is n eed ed (c) w r ite s w itch register via smi in terface (offset hex = 10?h180, data = 32?h1300_0000) ee sk ed i ( c p u ) z 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 z pr eam b l e s t a r t op c o d e (w ri t e ) r e g i s t er addr es s ( 1 0 ' h 180 i n t h i s e x am pl e) t a r e gi s t e r d a t a ( 3 2 ' h 1 3 0 0 000 0 i n t h i s e x a m pl e) 0 ~ ~ s m i w r i t e op era t i o n o n e mo re eesk i s n eed ed (d) the pin type of eecs, eesk, edi and edo during the operation. pin nam e reset op eration loa d ee prom w r ite op eration read ope r ation e e c s i npu t o u t p u t i npu t i npu t eesk i npu t o u t p u t i npu t i npu t ed i i npu t o u t p u t i npu t i npu t/o u t p u t edo i npu t i npu t i npu t i npu t admtek inc. 3-16 ADM6926 function description 3.2 eeprom register format the eeprom can be auto-detected by adm 6926 through the signature register . the ADM6926 supports c66 eeprom. after the eep rom i s loaded, the output pins of ADM6926 are tri-state and released to cpu. th e release tim e is about 30m s after end of reset . w h enever cpu m odifies the setti ng of c66, the new value will be written to ADM6926 at the sam e tim e. if cpu changes the port setting (dupl ex/speed/aen), the ADM6926 will restart the auto-neg otiation auto m a tically . eeprom format: admtek inc. 3-17 offset hex inde x bit 15 - 8 b i t 7 ? 0 ty p e def a ult lo w 0 h si gnat u r e r o 41 5 4 h 02 0 0h 02 0 1h h i gh 1 h g l ob al conf igur atio n r w 3 800 h lo w 2h po rt 0 c o nfi g u r at i on r w 80 f f h 02 0 2h 02 0 3h hi g h 3h po rt 1 c o nfi g u r at i on r w 80 f f h lo w 4h po rt 2 c o nfi g u r at i on r w 80 f f h 02 0 4h 02 0 5h hi g h 5h po rt 3 c o nfi g u r at i on r w 80 f f h lo w 6h po rt 4 c o nfi g u r at i on r w 80 f f h 02 0 6h 02 0 7h hi g h 7h po rt 5 c o nfi g u r at i on r w 80 f f h lo w 8h po rt 6 c o nfi g u r at i on r w 80 f f h 02 0 8h 02 0 9h hi g h 9h po rt 7 c o nfi g u r at i on r w 80 f f h lo w ah po rt 8 c o nfi g u r at i on r w 80 f f h 02 0a h 02 0 bh hi g h bh po rt 9 c o nfi g u r at i on r w 80 f f h lo w c h po rt 1 0 c o n f i g urat i o n r w 80 f f h 02 0c h 02 0 dh hi g h dh po rt 1 1 c o nfi g urat i o n r w 80 f f h lo w eh po rt 1 2 c o n f i g urat i o n r w 80 f f h 02 0e h 0 20f h hi g h fh po rt 1 3 c o n f i g urat i o n r w 80 f f h lo w 10 h po rt 1 4 c o n f i g urat i o n r w 80 f f h 02 1 0h 02 1 1 h hi g h 1 1h po rt 1 5 c o n f i g urat i o n r w 80 f f h lo w 12 h po rt 1 6 c o n f i g urat i o n r w 80 f f h 02 1 2h 02 1 3h hi g h 13 h po rt 1 7 c o n f i g urat i o n r w 80 f f h lo w 14 h po rt 1 8 c o n f i g urat i o n r w 80 f f h 02 1 4h 02 1 5h hi g h 15 h po rt 1 9 c o n f i g urat i o n r w 80 f f h lo w 16 h po rt 2 0 c o n f i g urat i o n r w 80 f f h 02 1 6h 02 1 7h hi g h 17 h po rt 2 1 c o n f i g urat i o n r w 80 f f h lo w 18 h po rt 2 2 c o n f i g urat i o n r w 80 f f h 02 1 8h 02 1 9h h i gh 1 9 h por t 23 c o nf igu r ation r w 8 0 f f h lo w 1ah po rt 2 4 c o n f i g urat i o n r w 80 f f h 02 1a h 02 1 bh hi g h 1b h po rt 2 5 c o n f i g urat i o n r w 80 f f h lo w 1 c h m i scel l a neous c o n f i g urat i o n r w 82 0 h 02 1c h 02 1 dh hi g h 1d h t o s pri o ri t y m a p vl an pri o ri t y m a p r w 0h lo w 1eh fo rwa r di ng g r ou p 0 o u t b ou n d p o rt m a p lo w r w f f ff h 02 1e h 0 21f h hi g h 1f h fo rwa r di ng g r ou p 0 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 20 h fo rwa r di ng g r ou p 1 o u t b ou n d p o rt m a p lo w r w f f f f h 02 2 0h 02 2 1h hi g h 21 h fo rwa r di ng g r ou p 1 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 22 h fo rwa r di ng g r ou p 2 o u t b ou n d p o rt m a p lo w r w f f f f h 02 2 2h 02 2 3h hi g h 23 h fo rwa r di ng g r ou p 2 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 24 h fo rwa r di ng g r ou p 3 o u t b ou n d p o rt m a p lo w r w f f f f h 02 2 4h 02 2 5h hi g h 25 h fo rwa r di ng g r ou p 3 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 26 h fo rwa r di ng g r ou p 4 o u t b ou n d p o rt m a p lo w r w f f f f h 02 2 6h 02 2 7h hi g h 27 h fo rwa r di ng g r ou p 4 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 28 h fo rwa r di ng g r ou p 5 o u t b ou n d p o rt m a p lo w r w f f f f h 02 2 8h 02 2 9h hi g h 29 h fo rwa r di ng g r ou p 5 o u t b ou n d p o rt m a p hi gh r w 3f fh ADM6926 function description admtek inc. 3-18 offset hex inde x bit 15 - 8 b i t 7 ? 0 ty p e def a ult lo w 2ah fo rwa r di ng g r ou p 6 o u t b ou n d p o rt m a p lo w r w f f f f h 02 2a h 02 2 bh hi g h 2b h fo rwa r di ng g r ou p 6 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 2ch fo rwa r di ng g r ou p 7 o u t b ou n d p o rt m a p lo w r w f f f f h 02 2c h 02 2 dh hi g h 2d h fo rwa r di ng g r ou p 7 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 2eh fo rwa r di ng g r ou p 8 o u t b ou n d p o rt m a p lo w r w f f f f h 02 2e h 0 22f h hi g h 2f h fo rwa r di ng g r ou p 8 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 30 h fo rwa r di ng g r ou p 9 o u t b ou n d p o rt m a p lo w r w f f f f h 02 3 0h 02 3 1h hi g h 31 h fo rwa r di ng g r ou p 9 o u t b ou n d p o rt m a p hi gh r w 3f fh lo w 32 h fo rwa r di ng g r ou p 1 0 out b o u n d p o rt m a p l o w r w f f f f h 02 3 2h 02 3 3h hi g h 33 h fo rwa r di ng g r ou p 1 0 out b o u n d p o rt m a p h i gh r w 3f fh lo w 34 h fo rwa r di ng g r ou p 1 1 o u t b ou nd p o rt m a p l o w r w f f f f h 02 3 4h 02 3 5h hi g h 35 h fo rwa r di ng g r ou p 1 1 o u t b ou nd p o rt m a p h i gh r w 3f fh lo w 36 h fo rwa r di ng g r ou p 1 2 out b o u n d p o rt m a p l o w r w f f f f h 02 3 6h 02 3 7h hi g h 37 h fo rwa r di ng g r ou p 1 2 out b o u n d p o rt m a p h i gh r w 3f fh lo w 38 h fo rwa r di ng g r ou p 1 3 out b o u n d p o rt m a p l o w r w f f f f h 02 3 8h 02 3 9h hi g h 39 h fo rwa r di ng g r ou p 1 3 out b o u n d p o rt m a p h i gh r w 3f fh low 3 a h forw ard i ng gr oup 1 4 ou tbou nd por t map low r w f f f f h 02 3a h 02 3 bh hi g h 3b h fo rwa r di ng g r ou p 1 4 out b o u n d p o rt m a p h i gh r w 3f fh lo w 3ch fo rwa r di ng g r ou p 1 5 out b o u n d p o rt m a p l o w r w f f f f h 02 3c h 02 3 dh hi g h 3d h fo rwa r di ng g r ou p 1 5 out b o u n d p o rt m a p h i gh r w 3f fh lo w 3eh fo rwa r di ng g r ou p 1 6 out b o u n d p o rt m a p l o w r w f f f f h 02 3e h 0 23f h hi g h 3f h fo rwa r di ng g r ou p 1 6 out b o u n d p o rt m a p h i gh r w 3f fh lo w 40 h fo rwa r di ng g r ou p 1 7 out b o u n d p o rt m a p l o w r w f f f f h 02 4 0h 02 4 1h hi g h 41 h fo rwa r di ng g r ou p 1 7 out b o u n d p o rt m a p h i gh r w 3f fh lo w 42 h fo rwa r di ng g r ou p 1 8 out b o u n d p o rt m a p l o w r w f f f f h 02 4 2h 02 4 3h hi g h 43 h fo rwa r di ng g r ou p 1 8 out b o u n d p o rt m a p h i gh r w 3f fh lo w 44 h fo rwa r di ng g r ou p 1 9 out b o u n d p o rt m a p l o w r w f f f f h 02 4 4h 02 4 5h hi g h 45 h fo rwa r di ng g r ou p 1 9 out b o u n d p o rt m a p h i gh r w 3f fh lo w 46 h fo rwa r di ng g r ou p 2 0 out b o u n d p o rt m a p l o w r w f f f f h 02 4 6h 02 4 7h hi g h 47 h fo rwa r di ng g r ou p 2 0 out b o u n d p o rt m a p h i gh r w 3f fh lo w 48 h fo rwa r di ng g r ou p 2 1 out b o u n d p o rt m a p l o w r w f f f f h 02 4 8h 02 4 9h hi g h 49 h fo rwa r di ng g r ou p 2 1 out b o u n d p o rt m a p h i gh r w 3f fh lo w 4ah fo rwa r di ng g r ou p 2 2 out b o u n d p o rt m a p l o w r w f f f f h 02 4a h 02 4 bh hi g h 4b h fo rwa r di ng g r ou p 2 2 out b o u n d p o rt m a p h i gh r w 3f fh lo w 4ch fo rwa r di ng g r ou p 2 3 out b o u n d p o rt m a p l o w r w f f f f h 02 4c h 02 4 dh hi g h 4d h fo rwa r di ng g r ou p 2 3 out b o u n d p o rt m a p h i gh r w 3f fh lo w 4eh fo rwa r di ng g r ou p 2 4 out b o u n d p o rt m a p l o w r w f f f f h 02 4e h 0 24f h hi g h 4f h fo rwa r di ng g r ou p 2 4 out b o u n d p o rt m a p h i gh r w 3f fh lo w 50 h fo rwa r di ng g r ou p 2 5 out b o u n d p o rt m a p l o w r w f f f f h 02 5 0h 02 5 1h hi g h 51 h fo rwa r di ng g r ou p 2 5 out b o u n d p o rt m a p h i gh r w 3f fh lo w 52 h fo rwa r di ng g r ou p 2 6 out b o u n d p o rt m a p l o w r w f f f f h 02 5 2h 02 5 3h hi g h 53 h fo rwa r di ng g r ou p 2 6 out b o u n d p o rt m a p h i gh r w 3f fh lo w 54 h fo rwa r di ng g r ou p 2 7 out b o u n d p o rt m a p l o w r w f f f f h 02 5 4h 02 5 5h hi g h 55 h fo rwa r di ng g r ou p 2 7 out b o u n d p o rt m a p h i gh r w 3f fh lo w 56 h fo rwa r di ng g r ou p 2 8 out b o u n d p o rt m a p l o w r w f f f f h 02 5 6h 02 5 7h hi g h 57 h fo rwa r di ng g r ou p 2 8 out b o u n d p o rt m a p h i gh r w 3f fh lo w 58 h fo rwa r di ng g r ou p 2 9 out b o u n d p o rt m a p l o w r w f f f f h 02 5 8h 02 5 9h hi g h 59 h fo rwa r di ng g r ou p 2 9 out b o u n d p o rt m a p h i gh r w 3f fh lo w 5ah fo rwa r di ng g r ou p 3 0 out b o u n d p o rt m a p l o w r w f f f f h 02 5a h 02 5 bh hi g h 5b h fo rwa r di ng g r ou p 3 0 out b o u n d p o rt m a p h i gh r w 3f fh lo w 5ch fo rwa r di ng g r ou p 3 1 out b o u n d p o rt m a p l o w r w f f f f h 02 5c h 02 5 dh hi g h 5d h fo rwa r di ng g r ou p 3 1 out b o u n d p o rt m a p h i gh r w 3f fh 02 5e h l o w 5 e h pv id shi f t p0 v i d r w 1 h ADM6926 function description offset hex inde x bit 15 - 8 ty p e def a ult b i t 7 ? 0 02 5 f h h i g h 5f h p1 v i d 1 h lo w 6 0 h p 2 v i d r w 1 h 02 6 0h 02 6 1h hi g h 6 1 h p3 v i d r w 1 h lo w 6 2 h p 4 v i d r w 1 h 02 6 2h 02 6 3h hi g h 6 3 h p5 v i d r w 1 h lo w 6 4 h p 6 v i d r w 1 h 02 6 4h 02 6 5h hi g h 6 5 h p7 v i d r w 1 h lo w 6 6 h p 8 v i d r w 1 h 02 6 6h 02 6 7h hi g h 6 7 h p9 v i d r w 1 h lo w 6 8 h p1 0 vi d r w 1 h 02 6 8h 02 6 9h hi g h 6 9 h p1 1 vi d r w 1 h lo w 6 a h p1 2 vi d r w 1 h 02 6a h 02 6 bh hi g h 6 b h p1 3 vi d r w 1 h lo w 6 c h p1 4 vi d r w 1 h 02 6c h 02 6 dh hi g h 6 d h p1 5 vi d r w 1 h lo w 6 e h p1 6 vi d r w 1 h 02 6e h 0 26f h hi g h 6 f h p1 7 vi d r w 1 h lo w 7 0 h p1 8 vi d r w 1 h 02 7 0h 02 7 1h hi g h 7 1 h p1 9 vi d r w 1 h lo w 7 2 h p2 0 vi d r w 1 h 02 7 2h 02 7 3h hi g h 7 3 h p2 1 vi d r w 1 h lo w 7 4 h p2 2 vi d r w 1 h 02 7 4h 02 7 5h hi g h 7 5 h p2 3 vi d r w 1 h lo w 7 6 h p2 4 vi d r w 1 h 02 7 6h 02 7 7h hi g h 7 7 h p2 5 vi d r w 1 h lo w 78 h p0, p 1 , p2 , p 3 b a nd wi dt h c o nt r o l r e gi st er r w 0h 02 7 8h 02 7 9h hi g h 79 h p4, p 5 , p6 , p 7 b a nd wi dt h c o nt r o l r e gi st er r w 0h lo w 7ah p8, p 9 , p1 0, p 1 1 b a n d w i d t h c ont r o l r e gi st er r w 0h 02 7a h 02 7 bh hi g h 7b h p1 2, p1 3, p 1 4 , p1 5 b a n d wi dt h c ont r o l r e gi st er r w 0h lo w 7ch p1 6, p1 7, p 1 8 , p1 9 b a n d wi dt h c ont r o l regi s t er r w 0h 02 7c h 02 7 dh hi g h 7d h p2 0, p2 1, p 2 2 , p2 3 b a n d wi dt h c ont r o l r e gi st er r w 0h lo w 7eh p2 5, p2 4 b a n d w i d t h c o nt r o l r e gi st er r w 0h 02 7e h 0 27f h hi g h 7f h b a nd wi dt h c o nt r o l ena b l e r e gi st er l o w r w 0h lo w 80 h b a nd wi dt h c o nt r o l ena b l e r e gi st er hi g h r w 0h 02 8 0h 02 8 1h hi g h 8 1 h r e serve d r w 0 h lo w 8 2 h r e serve d r w 0 h 02 8 2h 02 8 3h hi g h 8 3 h r e serve d r w 10 0 h lo w 8 4 h r e serve d r w 0 h 02 8 4h 02 8 5h hi g h 8 5 h r e serve d r w 0 h lo w 8 6 h r e serve d r w 0 h 02 8 6h 02 8 7h hi g h 8 7 h r e serve d r w 0 h lo w 8 8 h r e serve d r w 0 h 02 8 8h 02 8 9h hi g h 8 9 h r e serve d r w 0 h lo w 8 a h r e serve d r w f f 00 h 02 8a h 02 8 bh hi g h 8b h c u st om i zed ph y c o nt r o l gr ou p 0 r w 0h lo w 8ch c u st om i zed ph y c o nt r o l gr ou p 1 r w 0h 02 8c h 02 8 dh hi g h 8d h c u st om i zed ph y c o nt r o l gr ou p 2 r w 0h lo w 8eh c u st om i zed ph y c o nt r o l gr ou p 3 r w 0h 02 8e h 0 28f h hi g h 8f h gr o u p 0 p h y c u st om i zed d a t a 0 r w 0h lo w 90 h gr o u p 0 p h y c u st om i zed d a t a 1 r w 0h 02 9 0h 02 9 1h hi g h 91 h gr o u p 1 p h y c u st om i zed d a t a 0 r w 0h lo w 92 h gr o u p 1 p h y c u st om i zed d a t a 1 r w 0h 02 9 2h 02 9 3h hi g h 93 h gr o u p 2 p h y c u st om i zed d a t a 0 r w 0h r w admtek inc. 3-19 ADM6926 function description offset hex inde x bit 15 - 8 b i t 7 ? 0 ty p e def a ult lo w 94 h gr o u p 2 p h y c u st om i zed d a t a 1 r w 0h 02 9 4h 02 9 5h hi g h 95 h gr o u p 3 p h y c u st om i zed d a t a 0 r w 0h lo w 96 h gr o u p 3 p h y c u st om i zed d a t a 1 r w 0h 02 9 6h 02 9 7h hi g h 97 h ph y c u st om i z ed e n a b l e r e gi st er r w 0h lo w 98 h ppp oe c ont ro l r e gi st er 0 r w 0h 02 9 8h 02 9 9h hi g h 99 h ppp oe c ont ro l r e gi st er 1 r w 0h lo w 9ah ph y c ont rol r e gi st er 0 r w 0h 02 9a h 02 9 bh hi g h 9b h ph y c ont rol r e gi st er 1 r w 0h lo w 9ch di sabl e m d i o act i v e r e gi st e r 0 r w 0h 02 9c h 02 9 dh hi g h 9d h di sabl e m d i o act i v e r e gi st e r 1 r w 0h lo w 9eh di sabl e po rt r e gi st er 0 r w 0h 02 9e h 0 29f h hi g h 9f h di sabl e po rt r e gi st er 1 r w 0h lo w a0h igm p e n abl e r e gi st er 0 r w 0h 02a 0 h 02a 1 h hi g h a1h igm p e n abl e r e gi st er 1 r w 0h lo w a 2 h c p u c ont rol r e gi st e r r w 0 01f h 02a 2 h 02a 3 h hi g h a3h m a c f o r w ar d m o de r e gi st e r 0 r w 4h lo w a4h m a c f o r w ar d m o de r e gi st e r 1 r w 3h 02a 4 h 02a 5 h hi g h a5h m a c f o r w ar d m o de r e gi st e r 2 r w 0h lo w a6h t r u n k i n g e n ab l e r e gi st er 0 r w 0h 02a 6 h 02a 7 h hi g h a7h t r u n k i n g e n ab l e r e gi st er 1 r w 0h 3.2.1 signature (index: 0h) confi g ur ation descripti o n def a ult bit [1 5 : 0 ] th e v a lu e m u st b e at 4 154 h. adm 69 26 u s es th is v a lu e t o ch eck if t h e eeprom is attach ed . if th e v a lu e in t h e eepro m do esn? t equ a l to 4154 h, th e a d m 69 26 w ill not l o ad the e e prom e v e n i f the eepr o m is attached. 41 5 4h 3.2.2 global configuration register (in d ex: 1h) admtek inc. 3-20 confi g ur ation descripti o n def a ult b i t [1: 0 ] b r oa dcast s t or m thresh ol d. 2? b 00 bit [2 ] bro a d cast s t o r m fi lterin g enab le bit. 1 = th e adm 6 926 en ab les th e b r o a d cast st o r m filterin g fu n c tion . 0 = th e adm 6 926 d i sab l es t h e b r o a d cast st o r m filterin g fu n c tion . 1? b 0 bit [4 :3 ] priority qu eu e ratio . th e adm6 926 su ppo rt s two p r iorities on each o u t p u t po rt usi n g wei g ht ed r o u n d r o bi n sc hem e . the rat i o bet w ee n t h e l o w an d hi g h q u eue i s as fo llows: b i t [ 4: 3] r a t i o 00 1:2 01 1:4 10 1:8 1 1 1: 16 2? b 00 bit [8 :5 ] discard m o d e . th is fu n c tion en ab les th e s w i t ch to discard pack ets acc ording to t h eir pri o rities if the receivi ng port disables t h e flow c ont rol funct i on. users coul d use t h is to prev en t p a ck ets with th e low p r i o rity t o bl ock t h ose wi t h hi g h pri o ri t y . b i t [ 8: 7] = hi gh q u e u e di sc ard m o de (see sec. 3. 1. 1 8 ) bit[6:5] = low que u e disca r d mode. 4 ? b0 000 bit[9] c h e c k vl a n gr o u p . 1 = the adm 6926 will chec k if the pac k et s and the recei ving port are at t h e sam e forwa r di ng group. t h at is , the output port map for th e recei ving packet m u st co n t ain th e r e ceiv in g por t. if t h ey b e l o ng t o d i f f er en t fo rwar d i n g gr oup , t h e receiving pac k ets will be disc arde d. exam ple: port 3 receive s a packet a n d finds forwa r ding group contains p0, p1, and p 2 (d oes n ? t co nt ai n p 3 ). thi s packet wi l l be d r op pe d. 1? b 0 ADM6926 function description confi g ur ation descripti o n def a ult 0 = th e adm 6 926 will d i sab l e th e c h eck vlan group fun c tion . b i t [ 10] vl an g r o u p m ode . 1 = t h e s w i t c h i s c o nfi g u r ed t o t a gge d b a s e d vl an . 0 = th e switch is con f igured to port based vlan. 1? b 0 b i t [ 1 1 ] b y p a s s m o de. 1 = th e switch is con f igured to byp a ss mod e . th e p a ck et s will no t b e mo d i fied wh en t h ey are tran sm itted . 0 = t h e s w i t c h i s n o t co nfi g ure d t o b y pass m o de. 1? b 1 b i t [ 12] fo rce no t a g m ode . 1 = t h e s w i t c h i s c o nfi g u r ed t o f o rce no t a g m ode . i n t h i s m ode, t h e a d m 6 9 2 6 will n o t reco gnize th e vlan t a g ev en if t h ey co n t ain a t a g head er . 0 = t h e s w i t c h i s n o t co nfi g ure d t o f o rce no t a g m o de. 1? b 1 bit [1 3 ] leng th 15 36 en ab le b it. 1 = t h e s w itch ca n receive packets of less than 1536 bytes . 0 = t h e s w itch ca n receive packets of less then 1518 bytes . 1? b 1 b i t [ 14] fast m a na gem e nt c l oc k e n a b l e b i t . 1 = th e switch will u s e 10 m clo c k to configu r e t h e p h y s. 0 = th e switch will u s e 2 . 5m clo c k to configu r e t h e p h y s. 1? b 0 3.2.3 port configuration registers (index: 2h ~ 1bh) admtek inc. 3-21 confi g ur ation descripti o n def a ult bit [0 ] 1 0 b ase-t half du p l ex ab ilit y in au t o -nego tiatio n ad v e rtise m en t reg i ster . 1 = 1 0 b a se -t hal f d upl e x i s adve rt i s ed. 0 = 1 0 b a se -t hal f d upl e x i s not a d vert i s ed . 1? b 1 bit [1 ] 1 0 b ase-t fu ll dup l ex ab ility in au to -neg o t iatio n adv e rtise m en t reg i ster . 1 = 10 base-t fu ll dup l ex is ad v e rtised . 0 = 1 0 b a se -t ful l d u pl ex i s not a d vert i s ed . 1? b 1 bit [2 ] 1 0 0 b ase-tx half dup l ex ab ility in au t o -neg o tiatio n adv e rtise m en t reg i ster . 1 = 1 0 0 b a se- t x hal f d upl e x i s a d vert i s ed . 0 = 1 0 0 b a se- t x hal f d upl e x i s n o t ad vert i s ed. 1? b 1 bit [3 ] 1 0 0 b ase-tx fu ll du p l ex ab ility in au t o -neg o tiatio n adv e rtise m en t reg i ster . 1 = 100 base-tx fu ll dup l ex is adv e rtised. 0 = 1 0 0 b a se- t x ful l du pl e x i s n o t ad vert i s ed. 1? b 1 bit [4 ] 8 0 2 . 3x fl o w c o n t ro l ab ility i n fu ll dup l ex . 1 = (1 ). m a c c ont rol l e r su p p o r t s pause fram es whe n t h e po rt i s co nfi g u r e d t o by pa ss m a nagem e nt funct i o n fr om m d c / m d i o . (2 ). i f t h e p o rt i s n o t c o n f i g u r ed t o by pass m a nagem e nt f unct i o n f o rm m d c / m d i o , th en it will b e u s ed as th e pau s e b it in auto - n ego tiatio n ad v e rtisem en t reg i ster an d t h e pau s e fu n c tion will b e ad v e rtised. if au t o - n e got i a t i on f unct i o n i s di sabl e d , th en t h is b it is u s ed an d pau s e is supp orted. (3 ). if t h e p o rt i s n o t co nfi g u r ed t o by pass m a nagem e nt f u n c t i on fr om m d c / m d io an d no phy is attach ed to th is po rt, th e m a c con t ro ller will supp ort pau s e fram es in th e fu ll du p l ex . 0 = (1 ). m a c co nt r o l l e r does n ? t s u p p o rt pause f r am es when t h e p o rt i s c o nfi g ure d t o by pass m a nagem e nt fu nct i o n fr om m d c / mdi o . (2 ). i f t h e p o rt i s n o t c o n f i g u r ed t o by pass m a nagem e nt f unct i o n f o rm m d c / m d i o , th en it will b e u s ed as th e pau s e b it in auto - n ego tiatio n ad v e rtisem en t reg i ster an d th e pau s e fun c tion will no t b e adv e rt ised . if au to - n ego tiatio n fun c tio n is d i sab l ed , t h en th is b it is u s ed an d pau s e is no t su ppo rted. (3 ). if t h e p o rt i s n o t co nfi g u r ed t o by pass m a nagem e nt f u n c t i on fr om m d c / m d io an d no phy is attach ed to th is po rt, th e m a c con t ro ller will no t su ppo rt pau s e fram es in th e fu ll du p l ex . 1? b 1 ADM6926 function description confi g ur ation descripti o n def a ult admtek inc. 3-22 bit [5 ] au t o nego tiatio n en ab le i n b a sic mo d e contro l reg i ster . 1 = au t o -nego tiatio n is en ab led . 0 = aut o - n eg ot i a t i on i s di sa bl ed. 1? b 1 bit [6 ] sp eed ab ility . th is b it will b e u s ed as bit 13 (sp eed select) in th e basic m o d e c ont r o l r e gi st er i f by pa ss m a nagem e nt f unc t i on i s n o t ena b l e d, a n d be u s e d as s p eed desi re d i f by p a ss m a nagem e nt f u nct i o n i s e n abl e d. 1 = 100 mb /s en ab led . 0 = 10 m b /s en ab led . 1? b 1 bit [7 ] dup l ex ab ility . th is b it will be u s ed as bit 8 (dup lex select) in th e basic mo d e c ont r o l r e gi st er i f by pa ss m a nagem e nt f unc t i on i s n o t ena b l e d, a n d be u s e d as du pl ex de si re d i f by pass m a nagem e nt f unc t i on i s e n a b l e d. 1 = f u l l d upl e x e n a b l e d. 0 = hal f du pl ex e n a b l e d. 1? b 1 b i t [8] t a gge d po rt . 1 = th e tran smit ted po rt is co nfigu r ed t o a t a g g e d po rt. the tran sm itted p ack ets fro m a tag g e d po rt will always con t ain a t a g head er ex cep t th e tran sm itted p ack ets are m a nagem e nt pac k et or t h e b y pass m o d e i s ena b l e d . 0 = th e tran smit ted po rt is co nfigu r ed t o an un tagg ed port. th e transm i tte d p ack ets fro m an un tagged p o rt will n o t con t ain a t a g head er ex cep t th e tran sm i tted packet s are m a nagem e nt pac k et or t h e b y pa s s m o de i s e n a b l e d. 1? b 0 bit [9 ] security fun c tio n en ab le. 1 = t h e s w i t c h e n abl e s t h e s ecuri t y f unct i o n. fo u r sec u ri t y m odes c o ul d be sel ect ed th ro ugh bit[ 14:1 3 ] . 0 = t h e s w i t c h di sabl es t h e s ecuri t y f unct i o n. 1? b 0 bit [1 0 ] t o s ov er vlan priority . 1 = whe n the receiving pac k ets contain the ipv4 and t a g priority at the sa me time, th e switch will u s e ipv 4 priority field fo r th e q u e u e m a p p i ng. 0 = whe n the receiving pac k ets contain the ipv4 and t a g priority at the sa me time, th e switch will u s e t a g p r i o rity field for th e q u e u e m a p p i ng. 1? b 0 bit [1 1 ] en ab le po rt -b ase priority . 1 = th e switch will always use th e port-prio r ity fo r th e queu e m a p p i ng ev en if t h e receiving pac k ets contain ip v4 or t a g i n formation. 0 = th e switch will u s e t h e ipv4 o r t a g pr io rity field s fo r th e qu eu e m a p p i ng (see bit [1 0 ]). if t h e p a ck ets co n t ai n n o prio rity field , th en t h e switch will u s e t h e port-prio r ity for th e d e fau lt p r io rity . 1? b 0 bit [1 2 ] port-b ase priority map p i ng . 1 = mappe d for the high queue. 0 = mappe d for the l o w queue. 1? b 0 b i t [ 14: 1 3 ] fo ur sec u ri t y m ode . 0 0 = th e switch will fo rward p a ck ets with ?unk nown sou r ce addresses? to t h e c p u port and not learn it if the receiving po rt is configure d to e n a b le s ecurity function. t h e ?unknown source addres s? means that we can? t fi nd a n equal ad dr ess ex isted in t h e learn i ng tab l e an d its co rr esp ond ing po r t nu m b er equals to the recei ving port. this fu nction nee d s cpu? s hel p because we nee d t o create a ?static ad d r ess? to th e learn i ng tab l e fro m th e cpu. ?s tatic? m ean s th is ad dress will always ex ist in th e lean ing tab l e and can o n l y b e rem o ved throug h t h e cpu. whe n t h e a ddress is confi g ured to ? s ta tic?, we ca n pre v ent this a d dres s from o v e rlapp i ng wh en it is receiv ed fro m a p o rt with ou t t h e security fun c tio n enable d. 0 1 = th e switch will d i scard p ack ets with ?u nkn own source ad dresses? an d no t learn it if the recei ving port is c onfigure d to ena b le security function. only packets with sou r ce add r esses ex isted in th e learn i ng tab l e will b e fo rward e d . 10 = t he first receive d pac k e t s will be locked at the recei ving port if the receiving p o rt is co nfigured t o en ab le secu rity fu n c tion . on ly th e p a ck ets wit h th e sou r ce ad dress sam e a s th e l o ck ed one will b e fo rward e d and learned . 2? b 00 ADM6926 function description confi g ur ation descripti o n def a ult 1 1 = the first receive d pac k e t s will be locked as a b ove. the dif f e r ence is that the receiving port will not receive and learn pa ckets a n y m o re after the link goes do w n eve n i t l i nks up a g ai n (i t m a y happe n i f t h e st at i o n m oves t o t h e ot her po rt). bit[1 5 ] back pressu re en ab le bit. 1 = th e ma c co n t r o ller suppo r t s b a ck -p r e ssu r e fu n c tion i n h a lf du p l ex . 0 = t h e m a c cont rol l e r d o es n? t s u pp o r t bac k - p re ssu re fu n c t i on i n hal f du pl ex. 1? b 1 3.2.4 miscellaneous configuration (index: 1ch) confi g ur ation descripti o n def a ult bit[0 ] disab l e csm a /cd back-of f fun c tio n. 1 = th e mac co n t ro ller will d i sab l e rando m b a ck o f f fun c tio n. 0 = t h e m ac c ont rol l e r su p p o r t s ra n dom bac k of f fu nct i o n. 1? b 0 b i t [ 1] r ecom m e nd 1 6 th co llisio n drop . 1 = th e mac co n t ro ller will drop p a ck ets when th e co llision cou n t is lar g er th an 16 . 0 = th e mac co n t ro ller will retran sm it p ack ets ev en wh en th e co llision cou n t is lar g er th an 1 6 . 1? b 0 bit[2 ] r e s e r v ed 1 ? b0 bit[3 ] en ab le rep l ace vlan id 1 = the switch will replace t h e vid with t h e pvid associ ated with the receiving port whe n t h e received pac k ets a r e priority tagge d or its vid in the t a g hea d er equal s t o 1. 0 = th e switch will u s e t h e orig in al vid receiv ed fro m th e t a g head er . 1? b 0 b i t [ 7: 4] r e serve d 4? b 0 0 1 0 b i t [ 8] r e serve d 1? b 0 bit[9 ] co llisio n led en ab le. 1 = th e switch will p r ov id e t w o co llision leds fo r 10 m an d 100 m d o m ain i ndi vi dual l y an d fl ash i n rat e of 2 h z. 0 = th e switch will n o t provid e two co llisio n leds for 10 m an d 100 m d o m ain i ndi vi dual l y . 1? b 0 b i t [ 10] r e serve d 1? b 0 bit[1 1 ] r e s e r v ed 1 ? b0 b i t [ 12] r e serve d 1? b 0 b i t [ 13] r e serve d 1? b 0 3.2.5 vlan(tos) priority map (index: 1dh) admtek inc. 3-23 confi g ur ation descripti o n def a ult b i t [ 0] m a ppe d pri o ri t y que u e o f t a g v a l u e 0 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 1] m a ppe d pri o ri t y que u e o f t a g v a l u e 1 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 2] m a ppe d pri o ri t y que u e o f t a g v a l u e 2 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 3] m a ppe d pri o ri t y que u e o f t a g v a l u e 3 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 4] m a ppe d pri o ri t y que u e o f t a g v a l u e 4 1 = ma pp ed fo r h i g h qu eu e 0 = mapp ed fo r low qu eu e 1? b 0 b i t [ 5] m a ppe d pri o ri t y que u e o f t a g v a l u e 5 1? b 0 ADM6926 function description confi g ur ation descripti o n def a ult 1 = m a p p ed f o r t h e hi gh q u e u e 0 = ma ppe d for the l o w queue b i t [ 6] m a ppe d pri o ri t y que u e o f t a g v a l u e 6 1 = m a p p ed f o r t h e hi gh q u e u e 0 = ma ppe d for the l o w queue 1? b 0 b i t [ 7] m a ppe d pri o ri t y que u e o f t a g v a l u e 7 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 8] m a ppe d pri o ri t y que u e o f t o s 0 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 9] m a ppe d pri o ri t y que u e o f t o s 1 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 10] m a ppe d pri o ri t y que u e o f t o s 2 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 bit[1 1 ] map p e d priority qu eu e of t o s 3 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 12] m a ppe d pri o ri t y que u e o f t o s 4 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 13] m a ppe d pri o ri t y que u e o f t o s 5 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 14] m a ppe d pri o ri t y que u e o f t o s 6 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 b i t [ 15] m a ppe d pri o ri t y que u e o f t o s 7 1 = mappe d for the high queue 0 = mappe d for the l o w queue 1? b 0 3.2.6 forw arding group outbound port map lo w (index: 1eh, 20h, 22h, 24h, 26h, 28h, 2ah, 2ch, 2eh, 30h, 32h, 34h, 36h, 38h, 3ah, 3ch, 3eh, 40h, 42h, 44h, 46h, 48h, 4ah, 4ch, 4eh, 50h, 52h, 54h, 56h, 58h, 5ah, 5ch) admtek inc. 3-24 confi g ur ation descripti o n def a ult b i t [ 0] 1= p o rt 0 i s i n t h e f o r w ar di ng g r ou p 0 = p o rt 0 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 bit[1 ] 1 = port 1 is in th e fo rward i ng group 0 = p o rt 1 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 bit[2 ] 1 = port 2 is in th e fo rward i ng group 0 = p o rt 2 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 bit[3 ] 1 = port 3 is in th e fo rward i ng group 0 = p o rt 3 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 bit[4 ] 1 = port 4 is in th e fo rward i ng group 0 = p o rt 4 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 bit[5 ] 1 = port 5 is in th e fo rward i ng group 0 = p o rt 5 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 b i t [ 6] 1= p o rt 6 i s i n t h e f o r w ar di ng g r ou p, 0 = po rt 6 i s n o t i n t h e f o rwa r di ng g r o u p 1? b 1 b i t [ 7] 1= p o rt 7 i s i n t h e f o r w ar di ng g r ou p 0 = p o rt 7 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 b i t [ 8] 1= p o rt 8 i s i n t h e f o r w ar di ng g r ou p 1? b 1 ADM6926 function description confi g ur ation descripti o n def a ult 0 = p o rt 8 i s not i n t h e f o r w ardi ng g r o u p b i t [ 9] 1= p o rt 9 i s i n t h e f o r w ar di ng g r ou p 0 = p o rt 9 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 bit[1 0 ] 1 = po rt 10 is in th e forwardin g group 0 = por t 10 is no t in t h e forw ard i ng g r ou p 1? b 1 b i t [ 1 1 ] 1= p o rt 1 1 i s i n t h e f o r w ar di ng g r ou p 0 = p o rt 1 1 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 b i t [ 12] 1= po rt 12 i s i n t h e f o r w ar di ng g r ou p 0 = p o rt 1 2 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 b i t [ 13] 1= po rt 13 i s i n t h e f o r w ar di ng g r ou p 0 = p o rt 1 3 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 b i t [ 14] 1= po rt 14 i s i n t h e f o r w ar di ng g r ou p 0 = p o rt 1 4 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 b i t [ 15] 1= po rt 15 i s i n t h e f o r w ar di ng g r ou p 0 = p o rt 1 5 i s not i n t h e f o r w ardi ng g r o u p 1? b 1 3.2.7 forw arding group outbound port map high (index: 1fh, 21h, 23h, 25h, 27h, 29h, 2bh, 2dh, 2fh, 31h, 33h, 35h, 37h, 39h, 3bh, 3dh, 3fh, 41h, 43h, 45h, 47h, 49h, 4bh, 4dh, 4fh, 51h, 53h, 55h, 57h, 59h, 5bh, 5dh) confi g ur ation descripti o n def a ult bit[0 ] 1 = po rt 16 is in th e forwardin g group 0 = por t 16 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[1 ] 1 = po rt 17 is in th e forwardin g group 0 = por t 17 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[2 ] 1 = po rt 18 is in th e forwardin g group 0 = por t 18 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[3 ] 1 = po rt 19 is in th e forwardin g group 0 = por t 19 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[4 ] 1 = po rt 20 is in th e forwardin g group 0 = por t 20 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[5 ] 1 = po rt 21 is in th e forwardin g group 0 = por t 21 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[6 ] 1 = po rt 22 is in th e forwardin g group 0 = por t 22 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[7 ] 1 = po rt 23 is in th e forwardin g group 0 = por t 23 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[8 ] 1 = po rt 24 is in th e forwardin g group 0 = por t 24 is no t in t h e forw ard i ng g r ou p 1? b 1 bit[9 ] 1 = po rt 25 is in th e forwardin g group 0 = por t 25 is no t in t h e forw ard i ng g r ou p 1? b 1 3.2.8 p0 vid and pvid shift (index: 5eh ) admtek inc. 3-25 confi g ur ation descripti o n def a ult bit [1 1:0] po rt 0 vi d. t h e p o rt ? s de fa ult v i d is u s ed if th e fram e is un tagg ed or i f th e fram e ? s vid is 0x0000 or 0x0001 and e n able replace vl an id function (als o see m i scel l a neous c o n f i g urat i o n regi st er ) is en ab le d . 00 0 1h b i t [15: 13] vi d shi f t . t h i s f unct i o n m a ps 4 0 9 6 vl a n i n t o 32 f o r w ar di n g gr o ups . 1 . in t a gg ed b a sed vlan, the adm692 6 will u s e 5 b its fro m vid as th e ind e x to map in to fo rw ar d i n g gr oup s. 32 f o r w ard i ng gr oup s ar e d e f i ned in th e ad m 6 926 . w e use f0, f1, .f31 to call each fo rwarding group. t h is looking sc hem e is dif f ere n t from t h e p o rt b a se d vl an beca us e po rt b a se d v l a n uses p o rt num ber as t h e in de x t o ma p in to t h e forward i n g g ro u p s and th en f26 ~ f31 will no t b e used. th e vid is 3 ? b0 00 ADM6926 function description confi g ur ation descripti o n def a ult defi ned as fol l ow s: 1 . 1 th e po rt? s defau lt vid is used if th e fram e is no t 8 0 2 . 3 ac t a g g e d (no t a g heade r i n the fram e). 1 . 2 th e po rt? s defau lt vid is used if th e fram e is 802 .3 ac t a gged (t ag head er in the fram e) and the fram e? s vid is 0x 000 0 or 0x 000 1 and t h e en ab le rep l ace vl an i d fu nc t i on i s e n a b l e d. 1. 3 the vi d i n t h e t a g hea d er i s use d i f t h e fra m e i s 80 2. 3 t a gge d a n d t h e f r a m e ? s v i d is no t 0x00 00 or 0 x00 01 . 1. 4 the vi d i n t h e t a g hea d er i s use d i f t h e fra m e i s 80 2. 3 t a gge d a n d t h e f r a m e ? s v i d is 0x0 000 o r 0x0 001 and en ab le rep l ace v l an id fu n c tion is no t en ab led . 2 . th e relatio n b e tween vid sh ift, vid a nd th e f o r w ard i ng g r ou p is as fo llo ws: b i t [ 15: 1 3 ] f o r w ar di n g g r o up 00 0 = vi d [ 4: 0] 00 1 = vi d [ 5: 1] 01 0 = vi d [ 6: 2] 01 1 = vi d [ 7: 3] 10 0 = vi d [ 8: 4] 10 1 = vi d [ 9: 5] 1 1 0 = vi d [ 10:6] 1 1 1 = v i d [ 1 1 :7] 3.2.9 p1~p25 vi d configuration (index: 5fh, 60h, 61h, 62h, 63h, 64h, 65h, 66h, 67h, 68h, 69h, 6ah, 6bh, 6ch, 6dh, 6eh, 6fh, 70h, 71h, 72h, 73h, 74h, 75h, 76h, 77h) confi g ur ation descripti o n def a ult b i t [1 1: 0] the p o rt ? s def a ul t v i d 00 0 1h 3.2.10 p0, p1, p2, p3 bandw i dth control register (index: 78h) admtek inc. 3-26 confi g ur ation descripti o n por t 0 meter th r e sho l d c o n t ro l, d e f a u lt 000 00 0 0 0 1 01 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [2 :0 ] 64 k 12 8 k 2 5 6 k 5 1 2 k 1m 4m 10m 20m bit [3] port 0 receive packet le ngth counted on t h e sour ce port, default 0 0 = th e switch will add leng t h to th e p0 coun ter . por t 1 meter th r e sho l d c o n t ro l, d e f a u lt 000 00 0 0 0 1 01 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [6 :4 ] 64 k 12 8 k 2 5 6 k 5 1 2 k 1m 4m 10m 20m bit [7] port 1 receive packet le ngth counted on t h e sour ce port, default 0 0 = th e switch will add leng t h to th e p1 coun ter . por t 2 meter th r e sho l d c o n t ro l, d e f a u lt 000 00 0 0 0 1 01 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [10: 8] 64 k 12 8 k 2 5 6 k 5 1 2 k 1m 4m 10m 20m bit [1 1] port 2 receive packet le ngth counted on t h e s ource port, default 0 0 = th e switch will add leng t h to th e p2 coun ter . por t 3 meter th r e sho l d c o n t ro l, d e f a u lt 000 b i t [14: 12] 00 0 0 0 1 01 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 ADM6926 function description confi g ur ation descripti o n 64 k 12 8 k 2 5 6 k 5 1 2 k 1m 4m 10m 20m bit [15] port 3 receive packet le ngth counted on t h e s ource port, default 0 0 = th e switch will add leng t h to th e p3 coun ter . 3.2.11 p4, p5, p6, p7 bandw i dth control register (index: 79h) confi g ur ation descripti o n por t 4 meter th r e sho l d c o n t ro l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [2 :0 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [3] port 4 receive packet le ngth counted on t h e sour ce port, default 0 0 = th e switch will add leng t h to th e p4 coun ter . por t 5 meter th r e sho l d c o n t ro l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [6 :4 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [7] port 5 receive packet le ngth counted on t h e sour ce port, default 0 0 = th e switch will add leng t h to th e p5 coun ter . por t 6 meter th r e sho l d c o n t ro l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [10: 8] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [1 1] port 6 receive packet le ngth counted on t h e s ource port, default 0 0 = th e switch will add leng t h to th e p6 coun ter . po rt 7 m e ter thre sh old co n t rol, defa ult 0 0 0 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [14: 12] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [15] port 7 receive packet le ngth counted on t h e s ource port, default 0 0 = th e switch will add leng t h to th e p7 coun ter . 3.2.12 p8, p9, p10, p11 bandwidth control register (index: 7ah) admtek inc. 3-27 confi g ur ation descripti o n por t 8 meter th r e sho l d c o n t ro l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [2 :0 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [3] port 8 receive packet le ngth counted on t h e sour ce port, default 0 0 = th e switch will add leng t h to th e p8 coun ter . por t 9 meter th r e sho l d c o n t ro l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [6 :4 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [7] port 9 receive packet le ngth counted on t h e sour ce port, default 0 0 = th e switch will add leng t h to th e p9 coun ter . por t 10 meter th r e sho l d contr o l, d e f a u lt 000 b i t [10: 8] 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 ADM6926 function description confi g ur ation descripti o n 6 4 k 12 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [1 1] port 10 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p10 cou n t er . po rt 1 1 m e ter thre sh old co n t rol, defa ult 0 0 0 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [14: 12] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [15] port 1 1 recei ve packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p1 1 cou n t er . 3.2.13 p12, p13, p14, p15 bandw idth control register (index: 7b h) confi g ur ation descripti o n por t 12 meter th r e sho l d contr o l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [2 :0 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [3] port 12 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p12 cou n t er . por t 13 meter th r e sho l d contr o l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [6 :4 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [7] port 13 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p13 cou n t er . por t 14 meter th r e sho l d contr o l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [10: 8] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [1 1] port 14 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p14 cou n t er . por t 15 meter th r e sho l d contr o l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [14: 12] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [15] port 15 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p15 cou n t er . 3.2.14 p16, p17, p18, p19 bandw idth control register (index: 7ch) admtek inc. 3-28 confi g ur ation descripti o n por t 16 meter th r e sho l d contr o l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [2 :0 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [3] port 16 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p16 cou n t er . por t 16 meter th r e sho l d contr o l, d e f a u lt 000 bit [6 :4 ] 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 ADM6926 function description confi g ur ation descripti o n 6 4 k 12 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [7] port 17 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p17 cou n t er . por t 18 meter th r e sho l d contr o l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [10: 8] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [1 1] port 18 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p18 cou n t er . por t 19 meter th r e sho l d contr o l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [14: 12] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [15] port 19 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p19 cou n t er . 3.2.15 p20, p21, p22, p23 bandw idth control register (index: 7d h) confi g ur ation descripti o n por t 20 meter th r e sho l d contr o l, d e f a u lt 000 00 0 00 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [2 :0 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [3] port 20 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p20 cou n t er . por t 21 meter th r e sho l d contr o l, d e f a u lt 000 00 0 00 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [6 :4 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [7] port 21 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p21 cou n t er . por t 22 meter th r e sho l d contr o l, d e f a u lt 000 00 0 00 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [10: 8] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [1 1] port 22 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p22 cou n t er . por t 23 meter th r e sho l d contr o l, d e f a u lt 000 00 0 00 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 b i t [14: 12] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [15] port 23 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p23 cou n t er . 3.2.16 p24, p25 bandw i dth control register (index: 7eh) admtek inc. 3-29 confi g ur ation descripti o n por t 24 meter th r e sho l d contr o l, d e f a u lt 000 bit [2 :0 ] 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 ADM6926 function description confi g ur ation descripti o n 6 4 k 12 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [3] port 24 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p24 cou n t er . por t 25 meter th r e sho l d contr o l, d e f a u lt 000 00 0 0 0 1 0 1 0 0 1 1 10 0 1 0 1 1 1 0 1 1 1 bit [6 :4 ] 64 k 1 2 8 k 25 6 k 51 2 k 1m 4m 10m 20m bit [7] port 25 receive packet lengt h c o unted on t h e source port, de fault 0 0 = th e switch will add leng t h to th e p25 cou n t er . 3.2.17 bandw i dth control enable register low (index: 7fh) confi g ur ation descripti o n def a ult b i t [0] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 0. 1 = port 0 en ables th e b a ndwid th con t ro l. 0 = po rt 0 di sabl es t h e ba n d w i dt h c ont rol . 1? b 0 b i t [ 1] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1. 1? b 0 b i t [ 2] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 2. 1? b 0 b i t [ 3] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 3. 1? b 0 b i t [ 4] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 4 1? b 0 b i t [ 5] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 5 1? b 0 b i t [ 6] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 6 1? b 0 b i t [ 7] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 7 1? b 0 b i t [ 8] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 8 1? b 0 b i t [ 9] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 9 1? b 0 b i t [ 10] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 0 1? b 0 b i t [ 1 1 ] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 1 1? b 0 b i t [ 12] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 2 1? b 0 b i t [ 13] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 3 1? b 0 b i t [ 14] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 4 1? b 0 b i t [ 15] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 5 1? b 0 3.2.18 bandw i dth control enable register high (index: 80h) confi g ur ation descripti o n def a ult b i t [0] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 6 . 1? b 0 b i t [1] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 7 1? b 0 b i t [2] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 8 . 1? b 0 b i t [3] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 1 9 . 1? b 0 b i t [4] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 2 0 . 1? b 0 b i t [5] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 2 1 . 1? b 0 b i t [6] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 2 2 . 1? b 0 b i t [7] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 2 3 . 1? b 0 b i t [8] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 2 4 1? b 0 b i t [9] b a nd wi dt h c o nt r o l ena b l e fo r p o rt 2 5 . 1? b 0 3.2.19 reserved registers (in d ex: 81h~8ah) confi g ur ation descripti o n def a ult b i t [15: 0] r e serve d fo r t h e fut u re use a n d d o n ? t m odi f y t h e val u es. s ee s e c . 3.2 eep rom register admtek inc. 3-30 ADM6926 function description 3.2.20 customiz ed phy control group 0 (index: 8b h) confi g ur ation descripti o n def a ult b i t [4: 0 ] r e gi st er ad d r e ss o f t h e c o m m and 0. 5? b 0 0 0 00 bit [7 :5 ] phy ad dress o f th e c o mma n d 0 if bit[2 : 0 ] in phy c u stomized en ab le reg i ster = 3 ? b0 01 o r 3?b 0 1 1 . 0 0 0 = th e switch will write co mman d 0 in t o port 0 (phy ad dress = 3 2 ?h8). 0 0 1 = th e switch will write co mman d 0 in t o port 1 (phy ad dress = 3 2 ?h9). 0 1 0 = th e switch will write co mman d 0 in t o port 2 (phy ad dress = 3 2 ?h a). 01 1 = th e switch will write co mman d 0 in t o port 3 (phy ad dress = 3 2 ?hb). 1 0 0 = th e switch will write co mman d 0 in t o port 4 (phy ad dress = 3 2 ?h c). 1 0 1 = th e switch will write co mman d 0 in t o port 5 (phy ad dress = 3 2 ?hd). 1 1 0 = th e switch will write co mman d 0 in t o port 6 (phy ad dress = 3 2 ?h e). 1 1 1 = th e switch will write co mman d 0 in t o port 7 (phy ad dress = 3 2 ?hf). 3 ? b0 00 b i t [12: 8] r e gi st er ad d r e ss o f t h e c o m m and 1. 5? b 0 0 0 00 b i t [15: 13] ph y a d dress of t h e c o m m and 1 i f b i t [ 2: 0 ] i n ph y c u st om i zed ena b l e r e gi st er = 3 ? b0 10 o r 3?b 0 1 1 0 0 0 = th e switch will write co mman d 1 in t o port 0 (phy ad dress = 3 2 ?h8). 0 0 1 = th e switch will write co mman d 1 in t o port 1 (phy ad dress = 3 2 ?h9). 0 1 0 = th e switch will write co mman d 1 in t o port 2 (phy ad dress = 3 2 ?h a). 01 1 = th e switch will write co mman d 1 in t o port 3 (phy ad dress = 3 2 ?hb). 1 0 0 = th e switch will write co mman d 1 in t o port 4 (phy ad dress = 3 2 ?h c). 1 0 1 = th e switch will write co mman d 1 in t o port 5 (phy ad dress = 3 2 ?hd). 1 1 0 = th e switch will write co mman d 1 in t o port 6 (phy ad dress = 3 2 ?h e). 1 1 1 = th e switch will write co mman d 1 in t o port 7 (phy ad dress = 3 2 ?hf). 3 ? b0 00 note: the ADM6926 sup ports eight additi ona l commands for the customer to configur e the phy attached. four groups are defined and each gr oup shares two co mmands. group 0 contains p0, p1, p2, p3, p 4 , p5, p 6 and p7. group 1 c ontains p8, p 9 , p10 , p1 1, p12, p1 3, p 1 4 and p1 5. gr oup 2 contains p1 6, p17 , p1 8, p19, p2 0, p 2 1, p22 and p2 3. group 3 co ntains p24 an d p25. 3 bi ts enable register is associat ed with each group. e ach command is associated with a phy address, a register address, and data for writing. 3.2.21 customiz ed phy control group 1 (index: 8ch ) admtek inc. 3-31 confi g ur ation descripti o n def a ult b i t [4: 0 ] r e gi st er ad d r e ss o f t h e c o m m and 2. 5? b 0 0 0 00 b i t [7: 5 ] ph y ad d r ess of t h e c o m m and 2 (b i t [ 5: 3] i n p h y c u st om i zed enabl e r e gi st er = 3 ? b0 01 o r 3?b 0 1 1 ) 0 0 0 = th e switch will write co mman d 2 in t o port 8 (phy ad dress = 3 2 ?h10 ). 0 0 1 = th e switch will write co mman d 2 in t o port 9 (phy ad dress = 3 2 ?h1 1 ). 0 1 0 = th e switch will write co mman d 2 in t o port 1 0 (phy address = 32 ?h 12). 01 1 = th e switch will write co mman d 2 in t o port 1 1 (phy address = 32 ?h 13). 1 0 0 = th e switch will write co mman d 2 in t o port 1 2 (phy address = 32 ?h 14). 1 0 1 = th e switch will write co mman d 2 in t o port 1 3 (phy address = 32 ?h 15). 1 1 0 = th e switch will write co mman d 2 in t o port 1 4 (phy address = 32 ?h 16). 1 1 1 = th e switch will write co mman d 2 in t o port 1 5 (phy address = 32 ?h 17). 3 ? b0 00 b i t [12: 8] r e gi st er ad d r e ss o f t h e c o m m and 3. 5? b 0 0 0 00 b i t [15: 13] ph y ad d r ess of t h e c o m m and 3 (b i t [ 5: 3] i n p h y c u st om i zed enabl e r e gi st er = 3 ? b0 10 o r 3?b 0 1 1 ) 0 0 0 = th e switch will write co mman d 3 in t o port 8 (phy ad dress = 3 2 ?h10 ). 0 0 1 = th e switch will write co mman d 3 in t o port 9 (phy ad dress = 3 2 ?h1 1 ). 0 1 0 = th e switch will write co mman d 3 in t o port 1 0 (phy address = 32 ?h 12). 01 1 = th e switch will write co mman d 3 in t o port 1 1 (phy address = 32 ?h 13). 1 0 0 = th e switch will write co mman d 3 in t o port 1 2 (phy address = 32 ?h 14). 1 0 1 = th e switch will write co mman d 3 in t o port 1 3 (phy address = 32 ?h 15). 3 ? b0 00 ADM6926 function description confi g ur ation descripti o n def a ult 1 1 0 = th e switch will write co mman d 3 in t o port 1 4 (phy address = 32 ?h 16). 1 1 1 = th e switch will write co mman d 3 in t o port 1 5 (phy address = 32 ?h 17). 3.2.22 customiz ed phy control group 2 (index: 8d h) confi g ur ation descripti o n def a ult b i t [4: 0 ] r e gi st er ad d r e ss o f t h e c o m m and 4. 5? b 0 0 0 00 bit [7 :5 ] phy add r ess o f th e c o mma n d 4 (bit[8 : 6 ] in phy c u st o m ized en ab le reg i ster = 3 ? b0 01 o r 3?b 0 1 1 ) 0 0 0 = th e switch will write co mman d 4 in t o port 1 6 (phy address = 32 ?h 18). 0 0 1 = th e switch will write co mman d 4 in t o port 1 7 (phy address = 32 ?h 19). 0 1 0 = th e switch will write co mman d 4 in t o port 1 8 (phy address = 32 ?h 1 a ). 01 1 = th e switch will write co mman d 4 in t o port 1 9 (phy address = 32 ?h 1b). 1 0 0 = th e switch will write co mman d 4 in t o port 2 0 (phy address = 32 ?h 1 c ). 1 0 1 = th e switch will write co mman d 4 in t o port 2 1 (phy address = 32 ?h 1d). 1 1 0 = th e switch will write co mman d 4 in t o port 2 2 (phy address = 32 ?h 1 e ). 1 1 1 = th e switch will write co mman d 4 in t o port 2 3 (phy address = 32 ?h 1f). 3 ? b0 00 b i t [12: 8] r e gi st er ad d r e ss o f t h e c o m m and 5. 5? b 0 0 0 00 b i t [15: 13] ph y a d dress of t h e c o m m a nd 5 (b i t [ 8: 6] i n p h y c u st om i zed ena b l e r e gi st er = 3 ? b0 10 o r 3?b 0 1 1 ) 0 0 0 = th e switch will write co mman d 5 in t o port 1 6 (phy address = 32 ?h 18). 0 0 1 = th e switch will write co mman d 5 in t o port 1 7 (phy address = 32 ?h 19). 0 1 0 = th e switch will write co mman d 5 in t o port 1 8 (phy address = 32 ?h 1 a ). 01 1 = th e switch will write co mman d 5 in t o port 1 9 (phy address = 32 ?h 1b). 1 0 0 = th e switch will write co mman d 5 in t o port 2 0 (phy address = 32 ?h 1 c ). 1 0 1 = th e switch will write co mman d 5 in t o port 2 1 (phy address = 32 ?h 1d). 1 1 0 = th e switch will write co mman d 5 in t o port 2 2 (phy address = 32 ?h 1 e ). 1 1 1 = th e switch will write co mman d 5 in t o port 2 3 (phy address = 32 ?h 1f). 3 ? b0 00 3.2.23 customiz ed phy control group 3 (index: 8eh ) confi g ur ation descripti o n def a ult b i t [4: 0 ] r e gi st er ad d r e ss o f t h e c o m m and 6. 5? b 0 0 0 00 bit [5 ] phy address o f t h e co mm a n d 6 (bit[1 1 :9] in phy c u sto m ized en ab le reg i ster = 3 ? b0 01 o r 3?b 0 1 1 ) 0 = th e switch will write co mman d 6 in t o port 24 (phy add r ess = 32 ?h 6). 1 = th e switch will write co mman d 6 in t o port 25 (phy add r ess = 32 ?h 7). 3 ? b0 00 b i t [12: 8] r e gi st er ad d r e ss o f t h e c o m m and 7. 5? b 0 0 0 00 b i t [13] ph y ad d r ess of t h e c o m m and 7 (b i t [ 1 1 : 9 ] i n ph y c u st om i zed enabl e r e gi st er = 3 ? b0 10 o r 3?b 0 1 1 ) 0 = th e switch will write co mman d 7 in t o port 24 (phy add r ess = 32 ?h 6). 1 = th e switch will write co mman d 7 in t o port 25 (phy add r ess = 32 ?h 7). 3 ? b0 00 3.2.24 group 0 phy customiz ed data 0 (index: 8fh) confi g ur ation descripti o n def a ult b i t [15: 0] dat a f o r c o m m and 0 00 0 0h 3.2.25 group 0 phy customiz ed data 1 (index: 90h) confi g ur ation descripti o n def a ult b i t [15: 0] dat a f o r c o m m and 1 00 0 0h admtek inc. 3-32 ADM6926 function description 3.2.26 group 1 phy customiz ed data 0 (index: 91h) confi g ur ation descripti o n def a ult b i t [15: 0] dat a f o r c o m m and 2 00 0 0h 3.2.27 group 1 phy customiz ed data 1 (index: 92h) confi g ur ation descripti o n def a ult b i t [15: 0] dat a f o r c o m m and 3 00 0 0h 3.2.28 group 2 phy customiz ed data 0 (index: 93h) confi g ur ation descripti o n def a ult b i t [15: 0] dat a f o r c o m m and 4 00 0 0h 3.2.29 group 2 phy customiz ed data 1 (index: 94h) confi g ur ation descripti o n def a ult b i t [15: 0] dat a f o r c o m m and 5 00 0 0h 3.2.30 group 3 phy customiz ed data 0 (index: 95h) confi g ur ation descripti o n def a ult b i t [15: 0] dat a f o r c o m m and 6 00 0 0h 3.2.31 group 3 phy customiz ed data 1 (index: 96h) confi g ur ation descripti o n def a ult b i t [15: 0] dat a f o r c o m m and 7 00 0 0h 3.2.32 phy customiz ed enable register (index: 97h) admtek inc. 3-33 confi g ur ation descripti o n def a ult bit[2 : 0 ] phy c u sto m iz ed en ab le fo r grou p 0. 0 0 0 = disab l e writing ad d ition a l co mm an d s in to an y phys in gro u p 0 . 0 01 = w r ite co mman d 0 in t o related p o rt sp ecified b y t h e custo m ized phy con t ro l g r ou p 0. 0 10 = w r ite co mman d 1 in t o related p o rt sp ecified b y t h e custo m ized phy con t ro l g r ou p 0. 1 0 0 = disab l e writing ad d ition a l co mm an d s in to an y phys in gro u p 0 . 10 1 = w r i t e co m m a nd 0 i n t o al l phy s i n g r ou p 0. 1 1 0 = w r i t e co m m a nd 1 i n t o al l phy s i n g r ou p 0. 1 1 1 = w r i t e co m m a nd 0 a n d c o m m a nd 1 i n t o al l ph ys i n g r o u p 0. 3 ? b0 00 bit[5 : 3 ] phy c u sto m iz ed en ab le fo r grou p 1. 0 0 0 = disab l e writing ad d ition a l co mm an d s in to an y phys in gro u p 1 . 0 01 = w r ite co mman d 2 in t o related p o rt sp ecified b y t h e custo m ized phy con t ro l g r ou p 1. 0 10 = w r ite co mman d 3 in t o related p o rt sp ecified b y t h e custo m ized phy con t ro l g r ou p 1. 1 0 0 = disab l e writing ad d ition a l co mm an d s in to an y phys in gro u p 1 . 10 1 = w r i t e co m m a nd 2 i n t o al l phy s i n g r ou p 1. 1 1 0 = w r i t e co m m a nd 3 i n t o al l phy s i n g r ou p 1. 1 1 1 = w r i t e co m m a nd 2 a n d c o m m a nd 3 i n t o al l ph ys i n g r o u p 1. 3 ? b0 00 bit[8 : 6 ] phy c u sto m iz ed en ab le fo r grou p 2. 0 0 0 = disab l e writing ad d ition a l co mm an d s in to an y phys in gro u p 2 . 0 01 = w r ite co mman d 4 in t o related p or t s p ecified b y t h e custom ized phy control 3 ? b0 00 ADM6926 function description confi g ur ation descripti o n def a ult g r ou p 2. 0 10 = w r ite co mman d 5 in t o related p o rt sp ecified b y t h e custo m ized phy con t ro l g r ou p 2. 1 0 0 = disab l e writing ad d ition a l co mm an d s in to an y phys in gro u p 2 . 10 1 = w r i t e co m m a nd 4 i n t o al l phy s i n g r ou p 2. 1 1 0 = w r i t e co m m a nd 5 i n t o al l phy s i n g r ou p 2. 1 1 1 = w r i t e co m m a nd 5 a n d c o m m a nd 5 i n t o al l ph ys i n g r o u p 2. bit[1 1 : 9 ] phy c u sto m iz ed en ab le fo r grou p 3. 0 0 0 = disab l e writing ad d ition a l co mm an d s in to an y phys in gro u p 3 . 0 01 = w r ite co mman d 6 in t o related p o rt sp ecified b y t h e c usto m i zed phy con t ro l g r ou p 3. 0 10 = w r ite co mman d 7 in t o related p o rt sp ecified b y t h e custo m ized phy con t ro l g r ou p 3. 1 0 0 = disab l e writing ad d ition a l co mm an d s in to an y phys in gro u p 3 . 10 1 = w r i t e co m m a nd 6 i n t o al l phy s i n g r ou p 3. 1 1 0 = w r i t e co m m a nd 7 i n t o al l phy s i n g r ou p 3. 1 1 1 = w r i t e co m m a nd 6 a n d c o m m a nd 7 i n t o al l ph ys i n g r o u p 3. 3 ? b0 00 3.2.33 pppoe co ntrol register0 (index: 98h) confi g ur ation descripti o n def a ult bit [0 ] en ab le po rt 0 to t r ansm i t pppo e pack et only . th e adm69 26 will recogn ize p ack ets w ith leng th- t ype = 16? h88 63 or 1 6 ? h88 64 as t h e pppo e p a ck ets. 1 = the port 0 is configured to tra n sm it pppoe pac k ets onl y . 0 = th e po rt 0 is no t con f i g ured to tran sm i t pppoe p a ck ets on ly . 1? b 0 bit [1] ena b le p o rt 1 t o t r ansm it pppoe pac k et only . 1?b0 bit [2] ena b le p o rt 2 t o t r ansm it pppoe pac k et only . 1?b0 bit [3] ena b le p o rt 3 t o t r ansm it pppoe pac k et only . 1?b0 bit [4] ena b le p o rt 4 t o t r ansm it pppoe pac k et only . 1?b0 bit [5] ena b le p o rt 5 t o t r ansm it pppoe pac k et only . 1?b0 bit [6] ena b le p o rt 6 t o t r ansm it pppoe pac k et only . 1?b0 bit [7] ena b le p o rt 7 t o t r ansm it pppoe pac k et only . 1?b0 bit [8] ena b le p o rt 8 t o t r ansm it pppoe pac k et only . 1?b0 bit [9] ena b le p o rt 9 t o t r ansm it pppoe pac k et only . 1?b0 bit [10] ena b le p o rt 10 to t r ansm it pppoe pac k et only . 1?b0 bit [1 1] ena b le p o rt 1 1 to t r ansm it pppoe pac k et only . 1?b0 bit [12] ena b le p o rt 12 to t r ansm it pppoe pac k et only . 1?b0 bit[13] ena b le p o rt 13 to t r ansm it pppoe pac k et only . 1?b0 bit[14] ena b le p o rt 14 to t r ansm it pppoe pac k et only . 1?b0 bit[15] ena b le p o rt 15 to t r ansm it pppoe pac k et only . 1?b0 3.2.34 pppoe co ntrol register 1 (index: 99h) admtek inc. 3-34 confi g ur ation descripti o n def a ult bit [0] ena b le p o rt 16 to t r ansm it pppoe pac k et only . 1?b0 bit [1] ena b le p o rt 17 to t r ansm it pppoe pac k et only . 1?b0 bit [2] ena b le p o rt 18 to t r ansm it pppoe pac k et only . 1?b0 bit [3] ena b le p o rt 19 to t r ansm it pppoe pac k et only . 1?b0 bit [4] ena b le p o rt 20 to t r ansm it pppoe pac k et only . 1?b0 bit [5] ena b le p o rt 21 to t r ansm it pppoe pac k et only . 1?b0 bit [6] ena b le p o rt 22 to t r ansm it pppoe pac k et only . 1?b0 bit [7] ena b le p o rt 23 to t r ansm it pppoe pac k et only . 1?b0 bit [8] ena b le p o rt 24 to t r ansm it pppoe pac k et only . 1?b0 bit [9] ena b le p o rt 25 to t r ansm it pppoe pac k et only . 1?b0 b i t [ 10] ena b l e m a na g e m e nt packet c r oss pp po e por t fu nct i o n. 1? b 0 ADM6926 function description confi g ur ation descripti o n def a ult 1 = m a na gem e nt pac k et s c o ul d be t r a n sm i t t e d by any p o rt e v en i f i t i s c o n f i g u r ed t o ppp oe port. 0 = m a na gem e nt pac k et s c o ul d not be t r ans m i t t e d by t h e p ppo e po rt . 3.2.35 phy control regist er 0 (index: 9ah) descripti o n def a ult confi g ur ation bit[0 ] 1 = phy attach ed to po rt 0 acts as th e m a ster . th at is t h e switch will n o t co nfigu r e th e phy attached an d it will on ly po ll th e phy t o k now th e state th at phy ope rat e s. 0 = phy acts as th e slav e. the switch will use th e setting i n th e eepro m reg i ster to manage phy a ttached. 1? b 0 bit[1] 0 = phy acts a s the sla v e 1? b 0 1 = phy attached to port 2 a c ts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[3] 1 = phy attached to port 3 a c ts as the m a ster . 1? b 0 1 = phy attached to port 4 a c ts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[5] 1 = phy attached to port 5 a c ts as the m a ster . 1? b 0 1 = phy attached to port 6 a c ts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[7] 1 = phy attached to port 7 a c ts as the m a ster . 1? b 0 1 = phy attached to port 1 a c ts as the m a ster . bit[2] 0 = phy acts a s the sla v e. bit[4] 0 = phy acts a s the sla v e. bit[6] 0 = phy acts a s the sla v e. bit[8] 1 = phy attached to port 8 a c ts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[9] 1 = phy attached to port 9 a c ts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[1 0 ] 1 = phy attach ed to po rt 10 acts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[1 1 ] 1 = phy attached to port 1 1 acts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[1 2 ] 1 = phy attach ed to po rt 12 acts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 1 = phy attach ed to po rt 13 acts as the m a ster 0 = phy acts a s the sla v e. 1? b 0 bit[1 4 ] 1 = phy attach ed to po rt 14 acts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[1 5 ] 1 = phy attach ed to po rt 15 acts as the m a ster . 0 = phy acts a s the sla v e. 1? b 0 bit[1 3 ] 3.2.36 phy control regist er 1 (index: 9bh) admtek inc. 3-35 confi g ur ation descripti o n def a ult bit[0 ] 1 = phy attach ed to po rt 16 acts as the m a ster . 0 = phy actives as the slave . 1? b 0 bit[1 ] 1 = phy attach ed to po rt 17 acts as the m a ster . 0 = phy actives as the slave . 1? b 0 bit[2 ] 1 = phy attach ed to po rt 18 acts as the m a ster . 0 = phy actives as the slave . 1? b 0 bit[3 ] 1 = phy attach ed to po rt 19 acts as the m a ster . 0 = phy actives as the slave . 1? b 0 bit[4 ] 1 = phy attach ed to po rt 20 acts as the m a ster . 1?b0 ADM6926 function description confi g ur ation descripti o n def a ult 0 = phy actives as the slave . bit[5 ] 1 = phy attach ed to po rt 21 acts as the m a ster . 0 = phy actives as the slave . 1? b 0 bit[6 ] 1 = phy attach ed to po rt 22 acts as the m a ster 0 = phy actives as the slave . 1? b 0 bit[7 ] 1 = phy attach ed to po rt 23 acts as the m a ster . 0 = phy actives as the slave . 1? b 0 bit[8 ] 1 = phy attach ed to po rt 24 acts as the m a ster . 0 = phy actives as the slave . 1? b 0 bit[9 ] 1 = phy attach ed to po rt 25 acts as the m a ster . 0 = phy actives as the slave . 1? b 0 3.2.37 disable mdio active r e gister 0 (in d ex: 9ch) co nfigu r ation descri pt i on defa ul t b i t [ 0] po rt 0 b y pass m d i o f u nct i o n e n a b l e . 1 = by p a ss m d io en ab le. th e ef fect b y the fu n c tion is as fo llo ws: 1. 2 1. 3 1 . 4 1. 5 1. 6 li nk s t at us: p o rt 0 i s fo rce d t o l i nk up u n l ess t h e p o rt i s di sabl e d o r t h e spa nni ng t r ee i s i n di sabl e d st at e. spee d s t at us: p o rt 0 i s co nfi g u r ed t o b i t [6] i n t h e p o rt c o nfi g u r at i o n reg i ster . dup l ex s t atu s : port 0 is con f i g ured to bit [7 ] i n th e po rt c o nfiguratio n reg i ster . pause s t at us: po rt 0 i s co n f i g ure d t o b i t [4] i n t h e p o rt c o nfi g urat i on reg i ster . b ack p r ess u r e s t at us. p o r t 0 i s c o n f i g u r e d t o b i t [ 15] i n t h e po rt c o n f i g urat i o n r e gi st er . 0 = b y pass m d i o di sa bl e . the st at us i s dom i n at ed by t h e m d c / m d i o f u nct i o n except t h e l i n k up st at us, w h i c h m a y be di sab l ed, b y t h e p o rt di sabl e fu nct i on o r t h e s p an ni n g p r ot ocol . 1? b 0 b i t [ 1] po rt 1 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 2] po rt 2 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 3] po rt 3 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 4] po rt 4 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 5] po rt 5 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 6] po rt 6 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 7] po rt 7 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 8] po rt 8 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 9] po rt 9 b y pass m d i o f u nct i o n e n a b l e . 1? b 0 b i t [ 10] po rt 1 0 b y pa ss m d i o fu nct i o n e n abl e . 1? b 0 bit[1 1 ] port 1 1 by p a ss mdio fun c tio n en ab le. 1 ? b0 b i t [ 12] po rt 1 2 b y pa ss m d i o fu nct i o n e n abl e . 1? b 0 b i t [ 13] po rt 1 3 b y pa ss m d i o fu nct i o n e n abl e . 1? b 0 b i t [ 14] po rt 1 4 b y pa ss m d i o fu nct i o n e n abl e . 1? b 0 b i t [ 15] po rt 1 5 b y pa ss m d i o fu nct i o n e n abl e . 1? b 0 3.2.38 disable mdio active r e gister 1 (in d ex: 9dh) admtek inc. 3-36 confi g ur ation descripti o n def a ult bit[0 ] port 16 byp a ss mdio fun c tio n en ab le. 1 ? b0 bit[1 ] port 17 byp a ss mdio fun c tio n en ab le. 1 ? b0 bit[2 ] port 18 byp a ss mdio fun c tio n en ab le. 1 ? b0 bit[3 ] port 19 byp a ss mdio fun c tio n en ab le. 1 ? b0 bit[4 ] port 20 byp a ss mdio fun c tio n en ab le. 1 ? b0 ADM6926 function description confi g ur ation descripti o n def a ult bit[5 ] port 21 byp a ss mdio fun c tio n en ab le. 1 ? b0 bit[6 ] port 22 byp a ss mdio fun c tio n en ab le. 1 ? b0 bit[7 ] port 23 byp a ss mdio fun c tio n en ab le. 1 ? b0 bit[8 ] port 24 byp a ss mdio fun c tio n en ab le. 1 ? b0 bit[9 ] port 25 byp a ss mdio fun c tio n en ab le. 1 ? b0 3.2.39 port disable register 0 (index: 9eh ) confi g ur ation descripti o n def a ult bit [0] port 0 disa ble receive and t r ansm it. 1 = the port will not recei ve or transm i t pack ets. lea r ning is disable d in the disable d po rt . 0 = the port ac ts as the norm al m ode. 1? b 0 bit[1] port 1 disa ble r eceive and t r ansm it. 1?b0 bit[2] port 2 disa ble r eceive and t r ansm it. 1?b0 bit[3] port 3 disa ble r eceive and t r ansm it. 1?b0 bit[4] port 4 disa ble r eceive and t r ansm it. 1?b0 bit[5] port 5 disa ble r eceive and t r ansm it. 1?b0 bit[6] port 6 disa ble r eceive and t r ansm it. 1?b0 bit[7] port 7 disa ble r eceive and t r ansm it. 1?b0 bit[8] port 8 disa ble r eceive and t r ansm it. 1?b0 bit[9] port 9 disa ble r eceive and t r ansm it. 1?b0 bit[10] port 10 disabl e r eceive a n d t r ansm it. 1?b0 bit[1 1 ] port 1 1 disa ble receive a n d t r ansm it. 1?b0 bit[12] port 12 disabl e r eceive a n d t r ansm it. 1?b0 bit[13] port 13 disabl e r eceive a n d t r ansm it. 1?b0 bit[14] port 14 disabl e r eceive a n d t r ansm it. 1?b0 bit[15] port 15 disabl e r eceive a n d t r ansm it. 1?b0 3.2.40 port disable register 1 (index: 9fh ) confi g ur ation descripti o n def a ult bit[0] port 16 disabl e receive a n d t r ansm it. 1?b0 bit[1] port 17 disabl e receive a n d t r ansm it. 1?b0 bit[2] port 18 disabl e receive a n d t r ansm it. 1?b0 bit[3] port 19 disabl e receive a n d t r ansm it. 1?b0 bit[4] port 20 disabl e receive a n d t r ansm it. 1?b0 bit[5] port 21 disabl e receive a n d t r ansm it. 1?b0 bit[6] port 22 disabl e receive a n d t r ansm it. 1?b0 bit[7] port 23 disabl e receive a n d t r ansm it. 1?b0 bit[8] port 24 disabl e receive a n d t r ansm it. 1?b0 bit[9] port 25 disabl e receive a n d t r ansm it. 1?b0 3.2.41 igmp snooping control register 0 (index: a0h) admtek inc. 3-37 confi g ur ation descripti o n def a ult bit [0 ] port 0 en ab le igm p sn oop ing fu n c tion. th e p a ck ets with th e h e ad er (da = 0 100 5 e xx xxx x, len g t h _ t y p e = 0 800 , ip v e rsion = 4 , and pro t o c o l typ e = 2) will b e recogn ized as th e igm p p ackets, and t h e switch will fo rward it to th e cpu p o rt. 1 = t h e po rt 0 i s co nfi g u r e d t o e n abl e i g m p sn o opi ng f u n c t i on. th e port 0 is no t con f ig ured to en able igmp sno o p i ng fu n c tion . and th e igm p p ack ets will b e h a n d l ed as th e no rm al m u ltic ast p a ck ets. 1? b 0 bit[ 1 ] por t 1 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 ADM6926 function description confi g ur ation descripti o n def a ult bit[ 2 ] por t 2 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 bit[ 3 ] por t 3 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 bit[ 4 ] por t 4 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 bit[ 5 ] por t 5 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 bit[ 6 ] por t 6 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 bit[ 7 ] por t 7 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 bit[ 8 ] por t 8 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 bit[ 9 ] por t 9 en ab le ig mp snoo p i ng fun c tio n. 1 ? b0 b i t [ 10] po rt 1 0 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 1 1 ] po rt 1 1 ena b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 12] po rt 1 2 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 13] po rt 1 3 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 14] po rt 1 4 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 15] po rt 1 5 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 3.2.42 igmp snooping control register 1 (index: a1h) confi g ur ation descripti o n def a ult b i t [ 0] po rt 1 6 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 1] po rt 1 7 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 2] po rt 1 8 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 3] po rt 1 9 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 4] po rt 2 0 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 5] po rt 2 1 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 6] po rt 2 2 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 7] po rt 2 3 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 8] po rt 2 4 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 b i t [ 9] po rt 2 5 e n a b l e i g m p sn o opi ng f unct i o n. 1? b 0 bit[1 1 : 1 0 ] mu lticast co ntro l reg i ster . pack ets with th e fo llowing co nd itio ns wil l fo llow th e mu lticast co n t ro l reg i ster to h a nd le p ack ets. co nd itio n s : destin ation add r ess is n o t fo un d in t h e ad dress tab l e. and 2 . destin atio n ad dress is a m u lticast ad d r ess. and destin ation add r ess is n o t all 1 ? b1 . and dest i n at i o n a d dres s i s not a r e serve d a d dres s(0 1 80c 2 0 0 0 ~ ~ ). or igm p packets receive d by the port which dis a bles the igm p function. mu lticast co n t ro l actio n 00 = for w ar d t o all port s withi n th e same f o rw ar d i n g gr oup ex cep t t h e self por t. 01 = send to the c p u port. 10 = dis card. 1 1 = res e rve d . 1? b 0 3.2.43 cpu control regi ster (index: a2h ) admtek inc. 3-38 confi g ur ation descripti o n def a ult cpu por t nu mb er . th e ad m 6 926 allow s any p o r t to be confi g ured to be t h e cp u port. th e d e fau lt cpu p o rt is p o rt 31 . th at is c p u po rt is no t presen t. 0 000 0 = cpu p o r t is co nf igur ed to po r t 0 . 0 001 0 = cpu p o r t is co nf igur ed to po r t 2 . 0 000 1 = cpu p o r t is co nf igur ed to po r t 1 . 0 001 1 = cpu p o r t is co nf igur ed to po r t 3 . bit [4 :0 ] 0 010 0 = cpu p o r t is co nf igur ed to po r t 4 00 1 1 0 = c p u po rt i s c o n f i g u r ed t o p o rt 6. 0 010 1 = cpu p o r t is co nf igur ed to po r t 5 . 0 0 1 1 1 = c p u p o r t is co nf igur ed to po r t 7 . 5 ? b 1 1 111 ADM6926 function description confi g ur ation descripti o n def a ult 0 100 0 = cpu p o r t is co nf igur ed to po r t 8 . 0 101 0 = cpu p o r t is co nf igur ed to po r t 1 0 . 0 100 1 = cpu p o r t is co nf igur ed to po r t 9 . 0 101 1 = cpu p o r t is co nf igur ed to po r t 1 1 . 01 100 = cpu p o r t is co nf igur ed to po r t 1 2 01 1 1 0 = c p u p o r t is co nf igur ed to po r t 1 4 . 01 101 = cpu p o r t is co nf igur ed to po r t 1 3 . 01 1 1 1 = cpu p o r t is co nf igur ed to po r t 1 5 . 1 000 0 = cpu p o r t is co nf igur ed to po r t 1 6 . 1 001 0 = cpu p o r t is co nf igur ed to po r t 1 8 . 1 000 1 = cpu p o r t is co nf igur ed to po r t 1 7 . 1 001 1 = cpu p o r t is co nf igur ed to po r t 1 9 . 1 010 0 = cpu p o r t is co nf igur ed to po r t 2 0 10 1 1 0 = c p u po rt i s c o n f i g u r ed t o p o rt 22 . 1 010 1 = cpu p o r t is co nf igur ed to po r t 2 1 . 1 0 1 1 1 = c p u p o r t is co nf igur ed to po r t 2 3 . 1 1 000 = cpu p o r t is co nf igur ed to po r t 2 4 1 1 001 = cpu p o r t is co nf igur ed to po r t 2 5 . bit[5] ena b le receive 8-byte s p ecial tag fr om the c p u port t o s u pport igmp s n oopi ng, sp an n i n g tree or th e security fu n c tion . 1 = cpu will tran sm it p ack ets with add itio nal 8 - b y te sp eci al t a g and th e adm692 6 will rem o v e th i s sp ecial t a g , u s e i n fo rm atio n co n t ain e d t o forward p ack et s and recalculate crc value whe n this pac k et is re-transm i tted. 0 = cpu will tran sm it p ack ets as th e norm a l state. 1? b 0 bit[ 6 ] en ab le tr ansm i t 4 - b y te sp ecial tag to th e c p u p o r t to suppo r t i g m p sno o p i ng , sp ann i ng tree or th e security fun c tio n. 1 = a d m 6 926 w ill in sert additio n 4-b y te special t a g w h en it h a s p ack ets to b e tran sm it ted to t h e cpu po rt. 0 = a d m 6 926 w ill tran sm it p ack ets as t h e no rm al m o d e . 1? b 0 bit[7 ] en ab le in sert 4-b y te sp ecial tag wh en p a us e h a pp en s and bit[ 6 ] is e n ab le d. 1 = a d m 6 926 w ill add 4 - b y te sp ecial t a g w h en p a u s e h a p p e n s . 0 = a d m 6 926 w ill add 4 - b y te sp ecial t a g w h en p a u s e h a p p e n s . 1? b 0 b i t [ 10: 8] r e serve d . 3 ? b0 00 bit [1 2 : 1 1 ] learn i n g gro u p . adm692 6 has an ab ility to learn p a ck ets acco rd ing t h eir forward i ng g r ou p s . th e ad m692 6 cou l d b e d i v i d e d in t o 3 2 learn i ng gr oup s. w e use l0 , l1, ?and l31 to call each learning group. 0 x = n o rm al m ode, l earni ng wi t h s a onl y 10 = m a c cl one m ode, learning with sa a n d vid[0]. when packets are receive d a n d coul d be l ear ne d, t h ey are l ear ned di vi de d i n t o t w o g r o u p s. eve n f o rwa r di ng gr o ups are l ear ned i n t o l 0 a n d od d f o r w ar di ng g r ou ps a r e l earne d i n t o l 1 . 1 1 = lear ni n g wi t h s a an d v i d [ 4: 0] . whe n packet s are rec e i v ed a n d c oul d be l ear ne d, they are learne d acc ording t o t h ei r f o rwa r di n g gr o u p . t h at i s pac k et s bel o n g i n g t o f0 i s l earne d i n t o l0 , packet s bel o n g i n g t o f 1 i s l ear ne d i n t o l 1 , .., an d pa cket s b e lon g i n g to f3 1 is lean ed i n to l31 . 2? b 00 b i t [13] di sabl e c p u p o rt lea r ni n g f unct i o n. 1 = the packe t s receive d from th e cpu port will not be le arne d. 0 = the packe t s receive d from th e cpu port will be learne d. 1? b 0 3.2.44 special ma c for w ard control register 0 (in d ex: a3h) confi g ur ation descripti o n def a ult b i t [ 1: 0] the fo r w ar di n g opt i o n f o r de st i n at i on a d dre ss = 48 ? h 0 1 80c 20 0 0 0 0 0 (b pd u) 2? b 00 bit[ 3 : 2 ] th e fo rw ar d i ng op tion f o r destin atio n address = 0 180 c200 000 1 ( r eserved fo r pau s e ad dr ess) , m a c con t ro l f i eld = 88 08 , op c o de ! = 00 01 . 2? b 01 b i t [ 5: 4] the fo r w ar di n g opt i o n f o r de st i n at i on a d dre ss = 48 ? h 0 1 80c 20 0 0 0 0 2 (sl o w pr ot oc ol ) 2? b 00 bit[ 7 : 6 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 003 ( 802 .1 x p a e add r ess) 2 ? b0 0 bit[ 9 : 8 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 004 ~ 0 180 c20 000 0f 2 ? b0 0 bit[ 1 1 : 1 0 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 010 ~018 0 c 200 001 f 2 ? b0 0 bit[ 1 3 : 12 ] th e for w ar d i n g op tio n for d e stin ation ad dr ess = 0 180 c200 002 0~0 180 c200 0022 ( g mrp , gv rp , ga rp) 2? b 00 bit[ 1 5 : 14 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 023 ~018 0 c 200 00f f 2 ? b0 0 admtek inc. 3-39 ADM6926 function description note: 1. the options are defined here: 00 = the switch will forward the packets as the norm a l mode. that is for re serv ed addresse s ex isted in the learning table (becau s e reserved add r ess is m u ltic ast address, it could only be created through the cpu help if it really ex ists in the learning table). w e will use ?output po rt field? as th e inde x to lo okup the m u lticast tab l e. at las t , th e looked output port m a p (m ay be m o dified by th e forwarding process) is used as the output ports to forward packets. f o r rese rved addresses, whic h don? t exist in the learning table, it will be broa dcast to the forwarding group excep t the receiving port. 01 = the switch will discard the packets. 10 = the switch will f o rward the packets to th e cpu port. if the pac k et is r e ceiv ed from the cpu port, the p acket will be forwarded as the norm a l m ode. 1 1 = the switch will f o rward th e pa cket to cpu port. if th is packet is received from cpu port, this packe t will be d i sca r d. 2. the f o rwarding optio ns stated ab ove will be of no eff ect f o r the cpu port when u s ers enable the ?special tag function? a nd its output vector field is valid. 3.2.45 special ma c for w ard control register 2 (in d ex: a4h) confi g ur ation descripti o n def a ult b i t [ 1: 0] the fo r w ar di n g opt i o n f o r de st i n at i on a d dre ss = 48 ? h 0 1 80c 20 0 0 0 0 0 (b pd u) 2? b 1 1 b i t [ 3: 2] r e serve d . 2? b 00 b i t [ 5: 4] the fo r w ar di n g opt i o n f o r de st i n at i on a d dre ss = 48 ? h 0 1 80c 20 0 0 0 0 2 (sl o w pr ot oc ol ) 2? b 00 bit[ 7 : 6 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 003 ( 802 .1 x p a e add r ess) 2 ? b0 0 bit[ 9 : 8 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 004 ~ 0 180 c20 000 0f 2 ? b0 0 bit[ 1 1 : 1 0 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 010 ~018 0 c 200 001 f 2 ? b0 0 bit[ 1 3 : 12 ] th e fo rw ar d i n g op tio n f o r d e stin atio n ad dr ess = 0 180 c200 002 0 ~ 018 0 c 20 000 22 ( g mrp , gv rp , ga rp) 2? b 00 bit[ 1 5 : 14 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 023 ~018 0 c 200 00f f 2 ? b0 0 note: the ADM6926 will div i de packets into m a nage m e nt or unmanagem e nt packets. managem e nt packets will not be dropped even if the buffer is full for no flow control environm ent. only m a nagem e nt packets will be forwarded or r eceiv e d in blocking-n- listening o r the learn i ng state. the options are defined here: 00 = the packets will no t be cla ssif i e d as the m a nagem e nt packets and it will be tre a ted as the norm a l packet. 01 = the packets will be class i fied as the m a nagem e nt packets and it will be transm itted no m odified. 10 = the packets will be class i fied as the m a nagem e nt packets and it will be transm itted without tag. 11 = the packets will be class i fied as the m a nagem e nt packets and it will be transm itted with tag or without tag as the system configuration. 3.2.46 special ma c for w ard control register 2 (in d ex: a5h) admtek inc. 3-40 confi g ur ation descripti o n def a ult b i t [ 0] the fo r w ar di n g opt i o n f o r de st i n at i on a d dre ss = 48 ? h 0 1 80c 20 0 0 0 0 0 (b pd u) 1? b 0 bit[1 ] r e s e r v ed . 1? b 0 ADM6926 function description confi g ur ation descripti o n def a ult b i t [ 2] the fo r w ar di n g opt i o n f o r de st i n at i on a d dre ss = 48 ? h 0 1 80c 20 0 0 0 0 2 (sl o w pr ot oc ol ) 1? b 0 bit[ 3 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 003 ( 802 .1 x p a e add r ess) 1 ? b0 bit[ 4 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 004 ~ 0 180 c20 000 0f 1 ? b0 bit[ 5 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 010 ~018 0 c 200 001 f 1 ? b0 bit[ 6 ] th e f o r w ard i ng o p tion f o r d e stin ation add r ess = 0 180c2 000 020 ~0180 c200 002 2 ( g mrp , gv rp , ga rp) 1? b 0 bit[ 7 ] th e f o rw ard i ng o p tion fo r d e stin atio n add r ess = 0 180 c2000 023 ~018 0 c 200 00f f 1 ? b0 note: the options are defined here: 1 = the packets will cross forwarding group. 0 = the packets will not cross th e forwardin g packet. 3.2.47 trunking enable register 0 (index: a6h) confi g ur ation descripti o n def a ult bit[ 0 ] por t 0 t r u n k i ng en ab le. th e a d m 69 26 supp or ts o n e tru n k i ng p o r t . an y po r t cou l d b e assi gne d t o t h e t r u nki ng po rt . t h e t r u n k i n g fu nct i o n i s of t h e ef fec t onl y t h e trun k i n g h a rdware settin g = 1 . 1 = po rt 0 i s as si gne d t o a m e m b er of t h e t r u nki ng p o r t . 0 = port 0 is no t assign ed to a m e m b er o f the trunk ing p o rt. 1? b 0 b i t [ 1] 1 t r un ki n g e n a b l e . 1? b 0 b i t [ 2] 2 t r un ki n g e n a b l e . 1? b 0 b i t [ 3] 3 t r un ki n g e n a b l e . 1? b 0 b i t [ 4] 4 t r un ki n g e n a b l e . 1? b 0 b i t [ 5] 5 t r un ki n g e n a b l e . 1? b 0 b i t [ 6] 6 t r un ki n g e n a b l e . 1? b 0 b i t [ 7] 7 t r un ki n g e n a b l e . 1? b 0 b i t [ 8] 8 t r un ki n g e n a b l e . 1? b 0 b i t [ 9] 9 t r un ki n g e n a b l e . 1? b 0 bit[ 1 0 ] 1 0 t r unk in g en ab l e . 1 ? b0 b i t [ 1 1 ] 1 1 t r un ki ng e n abl e . 1? b 0 bit[ 1 2 ] 1 2 t r unk in g en ab l e . 1 ? b0 1 3 t r unk in g en ab l e . 1 ? b0 bit[ 1 4 ] 1 4 t r unk in g en ab l e . 1 ? b0 bit[ 1 5 ] 1 5 t r unk in g en ab l e . 1 ? b0 bit[ 1 3 ] 3.2.48 trunking enable register 1 (index: a7h) confi g ur ation descripti o n def a ult bit[ 0 ] 1 6 t r unk in g en ab l e . 1 ? b0 bit[ 1 ] 1 7 t r unk in g en ab l e . 1 ? b0 bit[ 2 ] 1 8 t r unk in g en ab le. 1 ? b0 bit[ 3 ] 1 9 t r unk in g en ab l e . 1 ? b0 bit[ 4 ] 2 0 t r unk in g en ab l e . 1 ? b0 bit[ 5 ] 2 1 t r unk in g en ab l e . 1 ? b0 bit[ 6 ] 2 2 t r unk in g en ab l e . 1 ? b0 bit[ 7 ] 2 3 t r unk in g en ab l e . 1 ? b0 bit[ 8 ] 2 4 t r unk in g en ab l e . 1 ? b0 bit[ 9 ] 2 5 t r unk in g en ab l e . 1 ? b0 admtek inc. 3-41 ADM6926 function description 3.3 sw itch register map offset hex bit 31 ~ 0 ty p e 0 h v e rsi o n i d r o 1 h l i nk s t at u s r o 2 h s p e e d s t at u s r o 3 h d u pl ex s t at u s r o 4 h f l ow c o nt r o l s t at u s r o 5h ad d r ess t a bl e c ont r o l r e gi st er 0 r w 6h ad d r ess t a bl e c ont r o l r e gi st er 1 r w 7h ad d r ess t a bl e c ont r o l r e gi st er 2 r w 8h ad d r ess t a bl e s t at us r e gi st er 0 r o 9h ad d r ess t a bl e s t at us r e gi st er 1 ro ah ro bh ph y c ont rol / s t a t u s r e gi st er r w ch r e s e r v ed r o d h h a r d w a r e s t at u s r o eh r x pkt ov erfl o w r o c f h r x l e n ove f lo w r o c 10 h t x p k t o v efl o w r o c 1 1 h t x l e n o v er fl o w r o c r x e r r ov erfl o w roc 1 3 h r x col ov erfl o w r o c r e new c o unt e r r e gi st er r w 15 h r ead c o u n t e r c ont r o l r e gi st er r w 16 h r ead c o u n t e r s t at us r e gi st er r o 17 h r e l o a d m d i o r e gi st e r r w 18h p0 ~ p15 spanning t r ee port s t ate r w 19 h p1 6 ~ p2 5 spa nni ng t r ee p o r t s t at e r w 1ah so urce p o rt r e gi st er r o 1b h t r ansm i t port r e gi st e r r w r o c 1d h b u f f er s t at us r e gi st er 1 r o c 1eh b u f f er s t at us r e gi st er 2 r o c 1f h b u f f er s t at us r e gi st er 3 r o c 1 xxh c o un ter reg i ster r w 2 xxh e e p r o m register address t a ble s t atus register 2 1 2 h 14 h 1ch b u f f er s t at us r e gi st er 0 r w 3.3.1 version id (offset: 0h) confi g ur ation def a ult b i t [ 19: 4] p r oject c o d e 16 ? h 3 1 1 0 b i t [ 3: 0] v e rsi o n c o d e 4? h 0 descripti o n 3.3.2 link status (offset: 1h ) admtek inc. 3-42 confi g ur ation descripti o n def a ult bit[ 0 ] por t 0 link s t atu s 1 = por t 0 links up . 0 = por t 0 links dow n. 1? b 0 b i t [ 1] po rt 1 li n k s t a t us 1? b 0 b i t [ 2] po rt 2 li n k s t a t us 1? b 0 b i t [ 3] po rt 3 li n k s t a t us 1? b 0 b i t [ 4] po rt 4 li n k s t a t us 1? b 0 b i t [ 5] po rt 5 li n k s t a t us 1? b 0 b i t [ 6] po rt 6 li n k s t a t us 1? b 0 ADM6926 function description confi g ur ation descripti o n def a ult b i t [ 7] po rt 7 li n k s t a t us 1? b 0 b i t [ 8] po rt 8 li n k s t a t us 1? b 0 po rt 9 li n k s t a t us 1? b 0 b i t [ 10] po rt 1 0 li nk s t at us 1? b 0 b i t [ 1 1 ] po rt 1 1 li n k s t at us 1? b 0 b i t [ 12] po rt 1 2 li nk s t at us 1? b 0 b i t [ 13] po rt 1 3 li nk s t at us 1? b 0 b i t [ 14] po rt 1 4 li nk s t at us 1? b 0 b i t [ 15] po rt 1 5 li nk s t at us 1? b 0 b i t [ 16] po rt 1 6 li nk s t at us 1? b 0 b i t [ 17] po rt 1 7 li nk s t at us 1? b 0 b i t [ 18] po rt 1 8 li nk s t at us 1? b 0 b i t [ 19] po rt 1 9 li nk s t at us 1? b 0 b i t [ 20] po rt 2 0 li nk s t at us 1? b 0 b i t [ 21] po rt 2 1 li nk s t at us 1? b 0 b i t [ 22] po rt 2 2 li nk s t at us 1? b 0 b i t [ 23] po rt 2 3 li nk s t at us 1? b 0 po rt 2 4 li nk s t at us 1? b 0 b i t [ 25] po rt 2 5 li nk s t at us 1? b 0 b i t [ 9] b i t [ 24] 3.3.3 speed status (offset: 2h) confi g ur ation descripti o n bit[0] port 0 speed s t atus 1 = po rt 0 ope r a t e s i n 10 0m . 0 = po rt 0 ope r a t e s i n 10m . 1? b 1 b i t [ 1] po rt 1 s p eed s t at us 1? b 1 1? b 1 b i t [ 3] po rt 3 s p eed s t at us 1? b 1 b i t [ 4] po rt 4 s p eed s t at us 1? b 1 b i t [ 5] po rt 5 s p eed s t at us 1? b 1 b i t [ 6] po rt 6 s p eed s t at us 1? b 1 b i t [ 7] po rt 7 s p eed s t at us 1? b 1 b i t [ 8] po rt 8 s p eed s t at us 1? b 1 b i t [ 9] po rt 9 s p eed s t at us 1? b 1 b i t [ 10] po rt 1 0 spee d s t at us 1? b 1 b i t [ 1 1 ] po rt 1 1 spee d s t at us 1? b 1 b i t [ 12] po rt 1 2 spee d s t at us 1? b 1 b i t [ 13] po rt 1 3 spee d s t at us 1? b 1 b i t [ 14] po rt 1 4 spee d s t at us 1? b 1 b i t [ 15] po rt 1 5 spee d s t at us 1? b 1 b i t [ 16] po rt 1 6 spee d s t at us 1? b 1 b i t [ 17] po rt 1 7 spee d s t at us 1? b 1 b i t [ 18] po rt 1 8 spee d s t at us 1? b 1 b i t [ 19] po rt 1 9 spee d s t at us 1? b 1 b i t [ 20] po rt 2 0 spee d s t at us 1? b 1 b i t [ 21] po rt 2 1 spee d s t at us 1? b 1 b i t [ 22] po rt 2 2 spee d s t at us 1? b 1 b i t [ 23] po rt 2 3 spee d s t at us 1? b 1 b i t [ 24] po rt 2 4 spee d s t at us 1? b 1 b i t [ 25] po rt 2 5 spee d s t at us 1? b 1 def a ult b i t [ 2] po rt 2 s p eed s t at us admtek inc. 3-43 ADM6926 function description 3.3.4 duplex status (offset: 3h) confi g ur ation descripti o n def a ult b i t [ 0] po rt 0 d u pl ex s t at us 1 = por t 0 o p e rates in fu ll duplex . 0 = po rt 0 ope r a t e s i n hal f du p l ex. 1? b 1 po rt 1 d u pl ex s t at us 1? b 1 po rt 2 d u pl ex s t at us 1? b 1 b i t [ 3] po rt 3 d u pl ex s t at us 1? b 1 b i t [ 4] po rt 4 d u pl ex s t at us 1? b 1 b i t [ 5] po rt 5 d u pl ex s t at us 1? b 1 b i t [ 6] po rt 6 d u pl ex s t at us 1? b 1 b i t [ 7] po rt 7 d u pl ex s t at us 1? b 1 b i t [ 8] po rt 8 d u pl ex s t at us 1? b 1 b i t [ 9] po rt 9 d u pl ex s t at us 1? b 1 b i t [ 10] po rt 1 0 d upl e x s t at us 1? b 1 b i t [ 1 1 ] po rt 1 1 d upl e x s t at us 1? b 1 po rt 1 2 d upl e x s t at us 1? b 1 b i t [ 13] po rt 1 3 d upl e x s t at us 1? b 1 b i t [ 14] po rt 1 4 d upl e x s t at us 1? b 1 b i t [ 15] po rt 1 5 d upl e x s t at us 1? b 1 b i t [ 16] po rt 1 6 d upl e x s t at us 1? b 1 b i t [ 17] po rt 1 7 d upl e x s t at us 1? b 1 b i t [ 18] po rt 1 8 d upl e x s t at us 1? b 1 b i t [ 19] po rt 1 9 d upl e x s t at us 1? b 1 b i t [ 20] po rt 2 0 d upl e x s t at us 1? b 1 b i t [ 21] po rt 2 1 d upl e x s t at us 1? b 1 b i t [ 22] po rt 2 2 d upl e x s t at us 1? b 1 b i t [ 23] po rt 2 3 d upl e x s t at us 1? b 1 b i t [ 24] po rt 2 4 d upl e x s t at us 1? b 1 b i t [ 25] po rt 2 5 d upl e x s t at us 1? b 1 b i t [ 1] b i t [ 2] b i t [ 12] 3.3.5 flow control status (offset: 4h) confi g ur ation descripti o n b i t [ 0] po rt 0 fl o w c o nt r o l s t at us r t 0 e n ab l e s pause f u nct i on i n ful l du pl ex or b ack pre ssu re f u nct i o n i n hal f du pl ex . 0 = po rt 0 di sabl es fl ow co nt r o l f u nct i o n . 1? b 1 b i t [ 1] po rt 1 fl o w c o nt r o l s t at us 1? b 1 b i t [ 2] po rt 2 fl o w c o nt r o l s t at us 1? b 1 b i t [ 3] po rt 3 fl o w c o nt r o l s t at us 1? b 1 b i t [ 4] po rt 4 fl o w c o nt r o l s t at us 1? b 1 b i t [ 5] po rt 5 fl o w c o nt r o l s t at us 1? b 1 b i t [ 6] po rt 6 fl o w c o nt r o l s t at us 1? b 1 b i t [ 7] po rt 7 fl o w c o nt r o l s t at us 1? b 1 b i t [ 8] po rt 8 fl o w c o nt r o l s t at us 1? b 1 b i t [ 9] po rt 9 fl o w c o nt r o l s t at us 1? b 1 b i t [ 10] po rt 1 0 fl o w c ont rol s t at us 1? b 1 b i t [ 1 1 ] po rt 1 1 fl o w c ont rol s t at us 1? b 1 b i t [ 12] po rt 1 2 fl o w c ont rol s t at us 1? b 1 b i t [ 13] po rt 1 3 fl o w c ont rol s t at us 1? b 1 b i t [ 14] po rt 1 4 fl o w c ont rol s t at us 1? b 1 b i t [ 15] po rt 1 5 fl o w c ont rol s t at us 1? b 1 b i t [ 16] po rt 1 6 fl o w c ont rol s t at us 1? b 1 po rt 1 7 fl o w c ont rol s t at us 1? b 1 b i t [ 18] po rt 1 8 fl o w c ont rol s t at us 1? b 1 def a ult b i t [ 17] admtek inc. 3-44 ADM6926 function description confi g ur ation descripti o n def a ult b i t [ 19] po rt 1 9 fl o w c ont rol s t at us 1? b 1 b i t [ 20] po rt 2 0 fl o w c ont rol s t at us 1? b 1 b i t [ 21] po rt 2 1 fl o w c ont rol s t at us 1? b 1 b i t [ 22] po rt 2 2 fl o w c ont rol s t at us 1? b 1 b i t [ 23] po rt 2 3 fl o w c ont rol s t at us 1? b 1 b i t [ 24] po rt 2 4 fl o w c ont rol s t at us 1? b 1 b i t [ 25] po rt 2 5 fl o w c ont rol s t at us 1? b 1 3.3.6 address table control and status register a ddress ta ble co nt ro l r e gist er 0 (off set: 5 h ), a ddress ta ble co nt rol r e g i st er 1 (of f set: 6 h ), a ddress ta ble co nt ro l r e gist er 2 (off set: 7 h ), a ddre s s table status regis t er 0 (offset: 8h ), addre ss t a bl e status re gister 1 (offset: 9h ), address table status regis t er 2 (offset: ah) the ADM6926 provid es custom co mmands t o access the a d dres s ta ble as well as the m u lticast output port map table. si x registers are us ed a n d they m e an diffe re ntly whe n differe n t tables are acce ssed. 3. 3. 6. 1 co ntr o l and s t a t us reg is ter for the addres s table. 1. the cont rol and status register description co ntr o l regis t er descripti o n c o m m a nd fi el d entry s t ate c ont r o l fi el d mu lticast ind e x fo rwa r di ng g r ou p ma c a d d r ess c ont r o l _ 2 [2: 0 ] c ont r o l _ 1 [3 1:3 0 ] c ont r o l _ 1 [2 9:2 6 ] co n t ro l_ l [2 5:2 1 ] c ont r o l _ 1 [2 0:1 6 ] {c ont r o l _ 1 [ 1 5 : 0] , c o nt r o l _ 0[ 31: 0] } out put po rt / admtek inc. 3-45 ADM6926 function description field description in the contr o l re gister field descripti o n m a c ad dre ss[ 47: 0] thi s fi el d i s 48 - b i t l a y e r 2 ad dress . t h e address could be the unicas t address or the m u lticas t address . fo rwa r di ng g r ou p [ 4: 0] thi s fi el d desc ri bes t h e lea r n i ng g r o u p t h e add r ess bel o n g s t o . o u tp u t por t [4 :0 ]/ m u l t i cast in de x[ 4: 0] thi s fi el d has t w o m eans. one i s desc ri b e d as t h e out p u t po rt a n d t h e ot her i s des c ri be d as t h e m u l ticast in d e x. th e s t atic bit. wh en t h is b it is set to a on e, th en th e add r ess en try will no t b e ag ed forev e r . th is b it coul d be c h an g e d onl y t h r o u g h t h e c p u? s he l p . en try s t ate[1 ] th is b it is u s ed to d i stin gu ish th e ou tpu t p o rt / m u lticast in d e x field . wh en a m a t c h (t he sa m e m a c a d d r ess a n d t h e sa m e fo rwa r di n g g r ou p i n t h e add r ess t a bl e) i s fo u n d , t h e val u e i n t h e out put po rt fi el d i s re t u r n ed as t h e o u t p ut p o rt , a n d m a y be m odi f i ed by t h e f o r w ard i ng g r ou p b e fo r e t h e pack et is tr an sf er r e d to th e ou tpu t qu eu e. wh en a m a t c h (t he sa m e m a c a d d r ess a n d t h e sa m e fo rwa r di n g g r ou p i n t h e add r ess t a bl e) i s f oun d, th e m u lticast o u t pu t po r t m a p en tr y ad dr essed by t h e m u l t i cast i ndex i s ret u r n e d as t h e out put po rt m a p, an d m a y be m odi fi ed by t h e fo rwa r di ng g r o u p bef o re t h e p acket i s t r a n sf erre d t o t h e out put q u eue . the c o mm and and control fiel ds a r e c o m b ined to pr o v i d e d i f f eren t op eratio ns. before th e op eration register . c o m m a nd fi el d c ont r o l fi el d ope r at i o n 01 1 1 create a ne w a d dress 00 0 1 1 1 1 ov erwrite an ex isted add r ess 00 1 1 1 1 1 e r a s e an ex is te d ad dr e s s 01 0 0 0 0 0 searc h a n em pty address 01 0 10 0 1 searc h by t h e po rt i n t h e o u t put po rt fi el d 01 0 1 0 1 0 searc h by the forwar d i ng gr ou p sp ecif i ed i n th e fo rw ard i ng g r ou p f i eld 010 1 1 00 searc h by the a d dress sp eci fied in the m a c address field. 01 0 1 1 1 0 searc h by t h e a d d r ess an d fo r w ar di n g gr o u p 01 0 1 1 0 1 searc h by t h e a d d r ess an d o u t put p o rt 01 0 10 1 1 searc h by t h e f o r w ar di n g g r o u p an d t h e out put p o rt 01 0 1 1 1 1 searc h by t h e a d d r ess , t h e f o r w ar di n g gr o u p and t h e o u t p ut po rt 01 1 0 100 in itial to lo cati o n b y t h e ad dress field c o m m a nd fi el d[ 2: 0] / c ont r o l fi el d [ 3: 0] 01 1 0 000 in itial to th e first add r ess en try s t ate[0 ] is in itiated , u s ers sho u l d co nfirm if th e search en g i n e is av ailab l e. see th e b u sy b it in th e statu s 000 s t atu s regi s t e r descri p t i o n co mman d resu lt bad s t ate entry s t ate occupy out put po rt / mu lticast ind e x fo rwa r di ng gr o up ma c a d d r ess st a t u s _ 2 [3] st a t u s _ 2 [2: 0 ] st a t u s _ 1 [2 9] st a t u s _ 1 [2 8:2 7 ] st a t u s _ 1 [2 6] st a t u s _ 1 [2 5:2 1 ] {s tatu s_1 [ 15 :0], s t atu s _0[ 31 : 0 ]} st a t u s _ 1 [2 0:1 6 ] bu sy admtek inc. 3-46 ADM6926 function description field description in the s t atus regis t er field descripti o n mac addre ss[47: 0] after the sea r c h opera tion is successful, the switch will ret u rn the ma c address in this field. if t h e search fails, t h is field does n? t mean anything. forwa r di ng group[4: 0] after the sea r c h op eration is successful, the sw itch will re turn t h e forwa r di ng group in this. if the search fails, t h is field does n? t mean anything. o u tp u t por t [4 :0 ]/ m u l t i cast in de x[ 4: 0] after the sea r c h ope ration is succes sful, the switch will re turn out p u t p o rt / m u lt icast i n d e x i n th is fi el d. t h e use r s co ul d use t h e ent r y _ st at e[1] ret u rne d t o di st i n g u i s h i f t h e ent r y s h oul d poi nt t o t h e m u l ticast o u t pu t port m a p tab l e. occupy after the searc h is successf ul, the switch will return the value indicating if the e n try e x isted. 1 = t h e s e a r che d en tr y ex is ts . 0 = the searc h ed e n try does n ? t exist. entry s t ate[0] after the sea r ch is successful, the switch w ill return the value i n this field indicating if value is static. 1 = t h e sea r c h ed ent r y is sta tic. 0 = th e search ed en t r y is not static an d will b e ag ed . en try s t ate[1 ] after th e search is su ccessfu l , th e switch will retu rn th e valu e in th is field ind i catin g if th e en try poi nt s t o t h e m u l t i cast out put po rt m a p t a bl e. 1 = th e en try po in ts t o th e m u l ticast o u t pu t port m a p tab l e. 0 = t h e e n t r y d o es n? t poi nt t o t h e m u l t i cast out put p o rt m a p t a bl e. bad s t ate after the searc h is succes sful, the switch will return the valu e indicating if the e n try is bad. 1 = t h e e n t r y i s ba d a n d i s n ? t use d f o r dat a st ora g e. 0 = th e en try is no t b a d and will b e u s ed for d a ta storag e. command res u lt[2: 0] this field indic a tes the access result. 00 0 = c o m m and o k 0 0 1 = all en try used . th is resu lt h a pp en s on ly fo r t h e c r ea t e ope rat i o n. a d m 6 9 2 6 use s t h e 4- way ad d r ess l o o k u p e n gi ne so i t al l o ws 4 di f f e r ent a d dresse s st ore d at eac h has h l o cat i o n. i f these 4 e n tries are all static, th en cpu will not su ccessfully create 5 th dif f erent a d dress h a sh ed to t h e sa m e lo catio n an d 001 will b e retu rn ed . th e on ly way to create 5 th di f f e r ent address is to rem ove one of early addres ses. 0 1 0 = en tr y no t fo und . 01 1 = t r y n e x t en tr y . 10 1 = c o m m and er r o r . busy this bit indicat es if the ta ble e ngi ne for acces s is available. 1 = the engine is busy a n d it will not acce ss the comm and from the cpu. 0 = the en gi ne i s avai l a bl e. 2. rules to access the a ddress table 2.1 check the busy bit in the status register to see if the access engine is availab l e. if the engine is busy, wait until the engine is free. if the engine is available, go to the following step. 2.2 w r ite the mac address[31:0] into the control register 0. 2.3 w r ite the mac address[47:32], forwar ding group, output po rt/multicast index, control field and the entry state into the con t rol regis t er 1. 2.4 w r ite the comm and into the control re gister 2 to define the operation. 2.5 w a it for the engine to com p lete (check the busy bit). 2.6 read the desired result return ed in the status register. admtek inc. 3-47 note: before the ?search command?, the cpu should execute the ?initial comm and? to initial the search poin t er. the search engine could search the aim from the top to th e bottom . the search eng i ne has an ab ility to au to m a tically move the poin t er to the ADM6926 function description associa t ed location (the result will b e retu rn ed). because m o re than one entry m a y match the searching condition (by port, by address, etc) at the sam e tim e, the cpu should continue to restart the search engin e un til the command result = entry not is found to confirm that no other m a tching entries exist. ma c 0 ma c 1 ma c 2 ma c 3 ma c 4 ma c 5 ma c 6 ma c 7 ma c 8 ma c 9 ma c 1 0 ma c 1 1 ma c 4084 ma c 4 085 ma c 408 6 ma c 4087 ma c 4088 ma c 4 089 ma c 409 0 ma c 4091 ma c 4092 ma c 4 093 ma c 409 4 ma c 4095 a ddr es s af t e r h a s h ed 0 1 2 1023 1022 1021 i n itia l to f i r s t a d d r e s s ( p oi nt e r j u m p s t o m a c 0) i n itia l to m a c 8 , m a c 9 , m a c 1 0 , m a c 1 1 ( p o i n t e r ju m p s to m a c 8 ) f i g u r e 3-1 t h e sear ch po inter 3. example admtek inc. 3-48 e xam pl e st e p the use r need s ad m692 6 to forwa r d the specified unicast packet ( d a = 48? h00 12 _34 56_ 789 a an d fo rwa r di ng g r ou p = 2 ) t o po r t 3 fo reve r . s t ep 1: c h ec k t h e b u sy bi t . if b u sy = 1? b 0 , go to th e step 2 . if b u sy = 1?b1 , wait. s t ep 2: w r i t e 3 2 ? h 34 5 6 _ 7 89a i n t o c ont rol re gi st er 0. s t ep 3 : w r ite 32 ?h5 c 62_ 001 2 in to th e con t ro l r e g i ster 1 . s t ep 4 : w r ite 32 ?h0 in t o th e co n t ro l reg i ster 2 to start the ? c reate? operati o n. s t ep 5: read the status registe r 2 to chec k t h e busy bit. i f b u sy = 1? b0, c h eck the command res u lt to see if the create ope ration is s u ccess f ul. if busy = 1?b1, wait for co m p letio n . the use r needs th e adm69 26 to forward th e specified m u ltica s t p ack et (d a = 4 8 ?h 012 3_4 567 _89 ab an d fo rw ard i ng g r ou p = 3 ) t o p o r t 5 onl y . t h i s a d dr ess co ul d be ag ed. s t ep 1: c h ec k t h e b u sy bi t . if b u sy = 1? b 0 , go to th e step 2 . if b u sy = 1?b1 , wait. s t ep 2: w r i t e 3 2 ? h 45 6 7 _ 8 9 ab i n t o c ont rol re gi st er 0. s t ep 3 : w r ite 32 ?h1 ca3_0 123 in to th e con t ro l reg i ster 1 . s t ep 4 : w r ite 32 ?h0 in t o th e co n t ro l reg i ster 2 to start the ? c reate? operati o n. s t ep 5: rea d the status regis t er 2 to ch eck th e bu sy b it. if b u sy = 1? b 0, c h eck t h e command res u lt to see if the create operat ion is s u ccess f ul. if b u sy = 1? b 1, wait fo r co m p letio n . ADM6926 function description e xam pl e st e p the use r want s t o kn o w ho w m a ny statio n s attach ed to port 4. s t ep 1: c h ec k t h e b u sy bi t . if b u sy = 1? b 0 , go to th e step 2 . if b u sy = 1?b1 , wait. s t ep 2 : w r ite 32 ?h0 000 _00 00 in to co n t r o l r e g i ster 1 . s t ep 3 : w r ite 3 2 ?h 000 0_0 003 i n to con t ro l reg i ster 2 t o start th e ?in itial to th e fi rst address? opera tion. s t ep 4: rea d the status regis t er 2 to ch eck th e bu sy b it. if b u sy = 1? b 0, c h eck t h e command result to see i f t h e initial op erat ion is successful. if busy = 1? b 1 , wait for co m p letio n . s t ep 5 : w r ite 32 ?h2 480 _00 00 i n t o c ont rol re gi st er 1. s t ep 6: w r i t e 3 2 ? h 0 0 0 0 _ 0 0 0 2 i n t o co nt r o l regi st er 2 t o st art t h e ?se a rch by po rt ? ope rat i o n. s t ep 7: rea d the status regis t er 2 to ch eck th e bu sy b it. if b u sy = 1? b 0, c h eck t h e command res u lt to see if the searc h operati o n is succes sful (the mac a d dress attache d t o p o rt 4 c o ul d be deri ved fr o m t h e m a c a d dres s i n t h e st a t us re gi st er ). if b u sy = 1? b 1, wait fo r co m p letio n . s t ep 8: i f c o m m a nd r e sul t = ?c om m a nd ok? , i t m eans som e ot her m a c ad dresse s attach ed to p o rt 4 m a y ex ist. w e shou ld rest art the ? s earc h by port? c o mmand a g ain t o l e t t h e searc h e ngi ne t o l o ok a not her ad dre s s e s. s t ep 9: if t h e c o m m a nd r e s u l t = ?ent ry not f o un d? , i t m eans no ot her a d dres ses attach ed to port 4 ex ist. 3. 3. 6. 2 co ntr o l and st a t us re gi ster f o r t h e mul t i c as t ou tp ut por t m a p t a bl e. 1. the cont rol and status register description co ntr o l regis t er descripti o n command field multica s t index c ont r o l _ 2 [ 2: 0] c ont r o l _ 0 [ 3 0 : 26] output p o rt map c ont r o l _ 0 [ 2 5 : 0 ] field description in the contr o l re gister field descripti o n out put po rt m a p thi s fi el d desc ri bes t h e out pu t po rt s ass o ci at ed wi t h t h e m u l t i cast i ndex. bit [0] is f o r p o rt 0, bit[1] is fo r po rt 1,. ., a n d bit[2 5 ] f o r p o rt 2 5 . m u l t i cast in de x see fi g u r e 3. 3. 6. 2. c o m m a nd fi el d 10 0 = c r eat e a n e n t r y i n t h e o u t p ut p o r t m a p t a bl e (i n d e x ed by t h e m u l t i cast in de x) . 1 0 1 = search an en try in th e ou tpu t port m a p tab l e (ind ex ed b y th e m u lticast ind e x ) . admtek inc. 3-49 ADM6926 function description un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 m u ltic a s t a d d r m u ltic a s t i n dex = 2 e n t r y s t at e[ 1 ] = 1 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 un i c a s t add r ou t p u t p o r t e n t r y s t at e[ 1 ] = 0 a d d r e ss ta b l e 25 2 4 2 1 0 ~ ~ m u ltic a s t in d e x 0 1 2 30 31 out p ut p o r t ma p m u ltic a s t o u tp ut p o r t m a p t a b l e f i g u r e 3-2 a d d r ess t a b l e map p i n g to ou tp u t po rt m a p s t atu s regi s t e r descri p t i o n busy co mma nd re sult output p o rt map s t atu s _2 [3 ] s t atu s _2 [2 :0 ] s t atu s _0 [25 : 0 ] field description in the s t atus regis t er field descripti o n ou t p u t port m a p th e con t en t asso ciated with t h e m u lticast in d e x will b e h e re after search ing . c o m m a nd r e s u l t 00 0 = c o m m and o k bu sy th is b it in d i cat es if th e ou tpu t po rt m a p eng i n e is av ailab l e. 1 = the engine is busy a n d it will not acce ss the comm and from the cpu. 0 = the en gi ne i s avai l a bl e. 2. rules to access the multicast o u tput port map table 2.1 check the busy bit to see if the access eng i ne is available. if the engin e is busy, w a it until the eng i ne is f r ee. if the engine is available, go to the f o llowing step. 2.2 w r ite ou tput port m a p and the multicas t index into the co ntrol regis t er 0. 2.3 w r ite the command into th e control register 2. 2.4 read the busy bit. if busy = 1?b1, wait. if busy = 1?b0, the operation com p letes. admtek inc. 3-50 ADM6926 function description 3. example e xam pl e st e p the use r needs th e adm69 26 to forward th e specified m u ltica s t p ack et (d a = 4 8 ?h 012 3_4 567 _89 ab an d fo rw ard i ng g r ou p = 3 ) t o p o r t 1 , po r t 2 an d por t 25 . th is addr ess coul d be a g ed . w e a ssum e t h e c p u want s t o wri t e out put p o rt m a p i n t o i nde x 1. s t ep 1: c h ec k t h e b u sy bi t . if b u sy = 1? b 0 , go to th e step 2 . if b u sy = 1?b1 , wait. s t ep 2 : w r ite 32 ?h0 060 _00 06 in to co n t r o l r e g i ster 0 . s t ep 3 : w r ite 32 ?h0 000 _00 04 in to co n t ro l reg i ster 2 start t h e ?w rite? co mman d . s t ep 4: c h ec k t h e b u sy bi t . if b u sy = 1? b 1 , wait. i f b u sy = 1?b1, go t o the ne xt step. s t ep 5: w r i t e 3 2 ? h 45 6 7 _ 8 9 ab i n t o c ont rol re gi st er 0. s t ep 6 : w r ite 32 ?h9 c 23_ 012 3 in to th e con t ro l r e g i ster 1 . s t ep 7 : w r ite 32 ?h0 in t o th e co n t ro l reg i ster 2 to start the ? c reate? operati o n. s t ep 8: rea d the status regis t er 2 to ch eck th e bu sy b it. if b u sy = 1? b 0, c h eck t h e command res u lt to see if the create operat ion is s u ccess f ul. if b u sy = 1? b 1, wait fo r co m p letio n . 3.3.7 phy control regi ster (offset: bh) confi g ur ation descripti o n def a ult bit[1 5 : 0 ] data field . th is field i n d i cates th e d a ta for read ing o r writin g. 1 6 ?h 0 b i t [ 20: 1 6 ] r e gi st er ad d r e s s 5? h 0 p o r t nu m b e r 5? h 0 b i t [ 26] c o m m a n d opt i on. 1 = r e a d 0 = w r ite 1? b 0 bit[2 7 ] access (busy) bit. 1 ? b0 bit[2 5 : 21 ] note: 1. this register allows the user to cont rol the phy attached through the cpu?s help. 2. rule for read operation: step 1: poll the busy bit (bit[27]) to check if the p hy control m odule is busy. step 2: w r ite the port number (bit[25: 21]), register address (bit[20:16]), command (bit[26]) and access bit(bit[ 27]) to start the read operation. step 3: poll the busy bit (b it[27]). if busy = 1?b1, wait. if busy = 1?b0, data is return ed in the data f i eld . 3. rule for w r ite operation: step 1: poll the busy bit (bit[27]) to check if the p hy control m odule is busy. step 2: w r ite the port number (bit[25: 21]), register address (bit[20:16]), command (bit[26]), data field (bit[ 15:0]) a nd access bit(bit[27]) to start the write operation. step 3: poll the busy bit (bit[27]). if busy = 1?b1, wait. if busy = 1?b0, writing operation completes. 4. exa m ple: the user wants to read th e basic control register in port 1. step 1: read bit[27] to check if phy m odule is in progress. step 2: if bit[27] = 1?b0, write bit[27 ] = 1?b1, bit[26] = 1? b1, bit[25:21] = 5?h1 and bit[20:16] = 5?h0. step 3: poll the busy bit. if bit[27] = 1?b0, data is retu rned in the data field. if bit[27] = 1?b1, wait. 3.3.8 hardw a re status (offset: dh) admtek inc. 3-51 confi g ur ation descripti o n def a ult bit[0] agi n g disa ble fr om hard war e pin 1 = a g i n g di sa bl e. 0 = a g i n g e n a b l e . hardware settin g bit[1 ] au t o -neg o tiatio n en ab le from hard ware pi n 1 = au to-negotiatio n en ab le. hardware settin g ADM6926 function description confi g ur ation descripti o n def a ult 0 = au to-negotiatio n disab l e. b i t [ 2] b ack p r ess u re ena b l e fr om har d ware pi n 1 = ba ck p r e s su r e e n ab le . 0 = b a c k press u re di sa bl e. hardware settin g b i t [ 3] fl ow c o nt r o l ena b l e f o r ful l du pl ex f r om har d ware pi n 1 = fl o w c ont rol e n a b l e . 0 = fl o w c ont rol di sabl e. hardware settin g bit[4 ] ipg 9 2 bit t i me en ab le from hard ware pi n 1 = ip g 92 e n able. 0 = ip g 9 2 disable. hardware settin g bit[5 ] t r unk ing en able fro m hardware 1 = t r un ki n g e n abl e . 0 = t r un ki n g di sabl e. hardware settin g b i t [ 7: 6] po rt 2 4 or p o rt 2 5 ope rat e i n r m ii or m i i m ode 00 = p o rt 2 4 a n d p o rt 2 5 are bot h c o n f i g ure d t o m i i m ode. 01 = p o rt 24 is confi g ured to rmii; po r t 25 is con f igur ed to mii . 10 = p o rt 2 4 is co nfi g u r ed to m ii; p o rt 2 5 is co nfi g u r ed to rm ii. 1 1 = port 24 a n d p o rt 25 a r e both c o nfi g ured to rmii . hardware settin g bit[8] bon d rm i i (s s-sm ii o r p u r e rm ii m o de) 1 = th e switch is in rmii p a ck ag e. 0 = th e switch is in ss-smii p ack ag e. hardware settin g 3.3.9 receive packet count overflow (offset: eh) confi g ur ation descripti o n def a ult bit[0 ] port 0 receive packet c o unt ove rfl ow . 1 = recei ve pa cket count in port 0 overfl ows and it will be cleared a f ter re ad from cpu. 1? b 0 bit[1] port 1 receive pack et c o unt ove rfl ow . 1?b0 bit[2] port 2 receive pack et c o unt ove rfl ow . 1?b0 bit[3] port 3 receive pack et c o unt ove rfl ow . 1?b0 bit[4] port 4 receive pack et c o unt ove rfl ow . 1?b0 bit[5] port 5 receive pack et c o unt ove rfl ow . 1?b0 bit[6] port 6 receive pack et c o unt ove rfl ow . 1?b0 bit[7] port 7 receive pack et c o unt ove rfl ow . 1?b0 bit[8] port 8 receive pack et c o unt ove rfl ow . 1?b0 bit[9] port 9 receive pack et c o unt ove rfl ow . 1?b0 bit[10] port 10 receive p acket c o unt overflow . 1?b0 bit[1 1 ] port 1 1 recei ve packet c o unt overflow . 1?b0 bit[12] port 12 receive p acket c o unt overflow . 1?b0 bit[13] port 13 receive p acket c o unt overflow . 1?b0 bit[14] port 14 receive p acket c o unt overflow . 1?b0 bit[15] port 15 receive p acket c o unt overflow . 1?b0 bit[16] port 16 receive p acket c o unt overflow . 1?b0 bit[17] port 17 receive p acket c o unt overflow . 1?b0 bit[18] port 18 receive p acket c o unt overflow . 1?b0 bit[19] port 19 receive p acket c o unt overflow . 1?b0 bit[20] port 20 receive p acket c o unt overflow . 1?b0 bit[21] port 21 receive p acket c o unt overflow . 1?b0 bit[22] port 22 receive p acket c o unt overflow . 1?b0 bit[23] port 23 receive p acket c o unt overflow . 1?b0 bit[24] port 24 receive p acket c o unt overflow . 1?b0 bit[25] port 25 receive p acket c o unt overflow . 1?b0 admtek inc. 3-52 ADM6926 function description 3.3.10 receive packet length count overflow (offset: fh) confi g ur ation descripti o n def a ult bit[0] port 0 receive pack et le ngth count ove rfl ow . 1 = receive packet length c o unt i n port 0 ove rfl ows a nd it will be clea red afte r read fr om cpu. 1? b 0 bit[1] port 1 receive packet le ngth count ove rfl ow 1?b0 port 2 receive packet le ngth count ove rfl ow 1?b0 bit[3] port 3 receive packet le ngth count ove rfl ow 1?b0 port 4 receive packet le ngth count ove rfl ow 1?b0 bit[5] port 5 receive packet le ngth count ove rfl ow 1?b0 port 6 receive packet le ngth count ove rfl ow 1?b0 bit[7] port 7 receive packet le ngth count ove rfl ow 1?b0 bit[8] port 8 receive packet le ngth count ove rfl ow 1?b0 bit[9] port 9 receive packet le ngth count ove rfl ow 1?b0 bit[10] port 10 receive packet lengt h c o unt ove rfl ow 1?b0 bit[1 1 ] port 1 1 recei ve packet lengt h c o unt ove rfl ow 1?b0 port 12 receive packet lengt h c o unt ove rfl ow 1?b0 bit[13] port 13 receive packet lengt h c o unt ove rfl ow 1?b0 bit[14] port 14 receive packet lengt h c o unt ove rfl ow 1?b0 bit[15] port 15 receive packet lengt h c o unt ove rfl ow 1?b0 bit[16] port 16 receive packet lengt h c o unt ove rfl ow 1?b0 bit[17] port 17 receive packet lengt h c o unt ove rfl ow 1?b0 bit[18] port 18 receive packet lengt h c o unt ove rfl ow 1?b0 bit[19] port 19 receive packet lengt h c o unt ove rfl ow 1?b0 bit[20] port 20 receive packet lengt h c o unt ove rfl ow 1?b0 port 21 receive packet lengt h c o unt ove rfl ow 1?b0 bit[22] port 22 receive packet lengt h c o unt ove rfl ow 1?b0 bit[23] port 23 receive packet lengt h c o unt ove rfl ow 1?b0 bit[24] port 24 receive packet lengt h c o unt ove rfl ow 1?b0 bit[25] port 25 receive packet lengt h c o unt ove rfl ow 1?b0 bit[2] bit[4] bit[6] bit[12] bit[21] 3.3.11 transmit p a cket count overflow (offset: 10h ) admtek inc. 3-53 confi g ur ation descripti o n def a ult bit[0] port 0 t r a n sm it packet c o unt ove rfl ow 1 = t r an sm i t p ack et coun t in p o rt 0 o v e rfl ows and it will b e cleared after read fro m cpu 1? b 0 bit[1 ] port 01 t r ansmit p acket count overflow 1?b0 b i t [ 2] po rt 2 t r a n sm it packet c o u n t ove rfl ow 1? b 0 b i t [ 3] po rt 3 t r a n sm it packet c o u n t ove rfl ow 1? b 0 b i t [ 4] po rt 4 t r a n sm it packet c o u n t ove rfl ow 1? b 0 b i t [ 5] po rt 5 t r a n sm it packet c o u n t ove rfl ow 1? b 0 b i t [ 6] po rt 6 t r a n sm it packet c o u n t ove rfl ow 1? b 0 b i t [ 7] po rt 7 t r a n sm it packet c o u n t ove rfl ow 1? b 0 b i t [ 8] po rt 8 t r a n sm it packet c o u n t ove rfl ow 1? b 0 b i t [ 9] po rt 9 t r a n sm it packet c o u n t ove rfl ow 1? b 0 bit[1 0 ] port 10 t r ansmit p acket count overflow 1?b0 bit[ 1 1 ] por t 1 1 t r an smit pack et count o v er f l o w 1 ? b0 bit[1 2 ] port 12 t r ansmit p acket count overflow 1?b0 bit[1 3 ] port 13 t r ansmit p acket count overflow 1?b0 bit[1 4 ] port 14 t r ansmit p acket count overflow 1?b0 bit[1 5 ] port 15 t r ansmit p acket count overflow 1?b0 bit[1 6 ] port 16 t r ansmit p acket count overflow 1?b0 bit[1 7 ] port 17 t r ansmit p acket count overflow 1?b0 bit[1 8 ] port 18 t r ansmit p acket count overflow 1?b0 ADM6926 function description confi g ur ation descripti o n def a ult bit[1 9 ] port 19 t r ansmit p acket count overflow 1?b0 bit[2 0 ] port 20 t r ansmit p acket count overflow 1?b0 bit[2 1 ] port 21 t r ansmit p acket count overflow 1?b0 bit[2 2 ] port 22 t r ansmit p acket count overflow 1?b0 bit[2 3 ] port 23 t r ansmit p acket count overflow 1?b0 bit[2 4 ] port 24 t r ansmit p acket count overflow 1?b0 bit[2 5 ] port 25 t r ansmit p acket count overflow 1?b0 3.3.12 transmit p a cket length count overflow (offset: 11h) confi g ur ation descripti o n def a ult bit[0 ] port 0 t r an sm i t pack et leng th c o un t ov erfl o w 1 = t r an sm i t p ack et leng th cou n t i n p o rt 0 ov erflows and it will b e cleared after read fr om cpu 1? b 0 bit[ 1 ] por t 1 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[ 2 ] por t 2 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[ 3 ] por t 3 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[ 4 ] por t 4 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[ 5 ] por t 5 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[ 6 ] por t 6 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[ 7 ] por t 7 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[ 8 ] por t 8 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[ 9 ] por t 9 t r an sm i t pack et leng th c o un t o v er f l o w 1 ? b0 bit[1 0 ] port 10 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 b i t [ 1 1 ] po rt 1 1 t r a n sm i t packet le ngt h c o u n t ove rfl ow 1? b 0 bit[1 2 ] port 12 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[1 3 ] port 13 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[1 4 ] port 14 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[1 5 ] port 15 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[1 6 ] port 16 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[1 7 ] port 17 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[1 8 ] port 18 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[1 9 ] port 19 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[2 0 ] port 20 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[2 1 ] port 21 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[2 2 ] port 22 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[2 3 ] port 23 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[2 4 ] port 24 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 bit[2 5 ] port 25 t r ansmit pack et leng th c o u n t ov erflow 1 ? b0 3.3.13 error count overflow (offset: 12h ) confi g ur ation descripti o n def a ult bit[0] po rt 0 er ro r c o u n t ove rfl ow 1 = err o r co unt in por t 0 ov erf l ow s an d it w i ll b e clear ed after r e ad f r o m c p u 1? b 0 bit[0] po rt 0 er ro r c o u n t ove rfl ow 1? b 0 bit[1] po rt 1 er ro r c o u n t ove rfl ow 1? b 0 bit[2] po rt 2 er ro r c o u n t ove rfl ow 1? b 0 bit[3] po rt 3 er ro r c o u n t ove rfl ow 1? b 0 po rt 4 er ro r c o u n t ove rfl ow 1? b 0 bit[5] po rt 5 er ro r c o u n t ove rfl ow 1? b 0 po rt 6 er ro r c o u n t ove rfl ow 1? b 0 bit[7] po rt 7 er ro r c o u n t ove rfl ow 1? b 0 bit[8] po rt 8 er ro r c o u n t ove rfl ow 1? b 0 bit[4] bit[6] admtek inc. 3-54 ADM6926 function description confi g ur ation descripti o n def a ult bit[9] po rt 9 er ro r c o u n t ove rfl ow 1? b 0 por t 10 er ror co un t o v er f l ow 1 ? b0 bit[1 1 ] po rt 1 1 er ro r cou n t ove rfl o w 1? b 0 bit[ 1 2 ] por t 12 er ror co un t o v er f l ow 1 ? b0 bit[ 1 3 ] por t 13 er ror co un t o v er f l ow 1 ? b0 bit[ 1 4 ] por t 14 er ror co un t o v er f l ow 1 ? b0 bit[ 1 5 ] por t 15 er ror co un t o v er f l ow 1 ? b0 bit[ 1 6 ] por t 16 er ror co un t o v er f l ow 1 ? b0 bit[ 1 7 ] por t 17 er ror co un t o v er f l ow 1 ? b0 bit[ 1 8 ] por t 18 er ror co un t o v er f l ow 1 ? b0 bit[ 1 9 ] por t 19 er ror co un t o v er f l ow 1 ? b0 bit[ 2 0 ] por t 20 er ror co un t o v er f l ow 1 ? b0 bit[ 2 1 ] por t 21 er ror co un t o v er f l ow 1 ? b0 bit[ 2 2 ] por t 22 er ror co un t o v er f l ow 1 ? b0 bit[ 2 3 ] por t 23 er ror co un t o v er f l ow 1 ? b0 bit[ 2 4 ] por t 24 er ror co un t o v er f l ow 1 ? b0 bit[ 2 5 ] por t 25 er ror co un t o v er f l ow 1 ? b0 bit[ 1 0 ] 3.3.14 collision c o unt overflow (offset: 13h) confi g ur ation descripti o n bit[0 ] port 0 co llision c o un t ov erfl o w . 1 = c o llisio n co un t in po rt 0 ov erflows a nd it will b e cleared after read fro m cpu. 1? b 0 bit[1 ] port 1 co llision c o un t ov erfl o w . 1 ? b0 bit[2 ] port 2 co llision c o un t ov erfl o w . 1 ? b0 bit[3 ] port 3 co llision c o un t ov erfl o w . 1 ? b0 bit[4 ] port 4 co llision c o un t ov erfl o w . 1 ? b0 bit[5 ] port 5 co llision c o un t ov erfl o w . 1 ? b0 bit[6 ] port 6 co llision c o un t ov erfl o w . 1 ? b0 bit[7 ] port 7 co llision c o un t ov erfl o w . 1 ? b0 bit[8 ] port 8 co llision c o un t ov erfl o w . 1 ? b0 bit[9 ] port 9 co llision c o un t ov erfl o w . 1 ? b0 bit[1 0 ] port 10 c o llisio n coun t ov erflo w . 1 ? b0 bit[1 1 ] port 1 1 c o llisio n coun t ov erflo w . 1 ? b0 bit[1 2 ] port 12 c o llisio n coun t ov erflo w . 1 ? b0 bit[1 3 ] port 13 c o llisio n coun t ov erflo w . 1 ? b0 bit[1 4 ] port 14 c o llisio n coun t ov erflo w . 1 ? b0 bit[1 5 ] port 15 c o llisio n coun t ov erflo w . 1 ? b0 bit[1 6 ] port 16 c o llisio n coun t ov erflo w . 1 ? b0 bit[1 7 ] 1 ? b0 bit[1 8 ] port 18 c o llisio n coun t ov erflo w . 1 ? b0 bit[1 9 ] port 19 c o llisio n coun t ov erflo w . 1 ? b0 port 20 c o llisio n coun t ov erflo w . 1 ? b0 bit[2 1 ] port 21 c o llisio n coun t ov erflo w . 1 ? b0 bit[2 2 ] port 22 c o llisio n coun t ov erflo w . 1 ? b0 bit[2 3 ] port 23 c o llisio n coun t ov erflo w . 1 ? b0 bit[2 4 ] port 24 c o llisio n coun t ov erflo w . 1 ? b0 bit[2 5 ] port 25 c o llisio n coun t ov erflo w . 1 ? b0 def a ult port 17 c o llisio n coun t ov erflo w . bit[2 0 ] admtek inc. 3-55 ADM6926 function description 3.3.15 rene w counter register (offset: 14h) note: 1. this register allows the user to rese t all counters f o r the co rresponding port. if the renew counter m odule is busy all oth e r m o dules about counters are not accessib l e. 2. rule: step 1: poll the busy bit to check if the renew counter m odule is busy. step 2: if the renew counter m odule is available, write th e port (bit[25:0]) the user wants to reset and the busy bit(bit[26]) to 1. step 3: poll the busy bit to check if th e renew counter m odule com p letes the job. 3. exa m ple: users want to reset p0, p 1, p2, p3 corresponding counters. step 1: read bit[26] to check if reset is in progress. step 2: if bit[26] = 0, wr ite bit[26] = 1?b1, bit[25:0] = 26?b00_0000_0000_0000_0000_0000_1111 into the register. step 3: poll the busy bit to check if reset com p letes admtek inc. 3-56 confi g ur ation descripti o n def a ult 1 = c l ear p o rt 0 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 1] 1 = c l ear p o rt 1 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 2] 1 = c l ear p o rt 2 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 3] 1 = c l ear p o rt 3 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 4] 1 = c l ear p o rt 4 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 5] 1 = c l ear p o rt 5 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 6] 1 = c l ear p o rt 6 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 7] 1 = c l ear p o rt 7 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 8] 1 = c l ear p o rt 8 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 9] 1 = c l ear p o rt 9 c o r r esp o ndi ng c o u n t e rs 1? b 0 b i t [ 10] 1 = c l ear p o rt 10 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 1 1 ] 1 = c l ear p o rt 1 1 c o rre sp o n d i ng c o unt er s 1? b 0 b i t [ 12] 1 = c l ear p o rt 12 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 13] 1 = c l ear p o rt 13 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 14] 1 = c l ear p o rt 14 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 15] 1 = c l ear p o rt 15 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 16] 1 = c l ear p o rt 16 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 17] 1 = c l ear p o rt 17 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 18] 1 = c l ear p o rt 18 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 19] 1 = c l ear p o rt 19 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 20] 1 = c l ear p o rt 20 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 21] 1 = c l ear p o rt 21 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 22] 1 = c l ear p o rt 22 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 23] 1 = c l ear p o rt 23 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 24] 1 = c l ear p o rt 24 c o rres p on d i ng c o unt er s 1? b 0 b i t [ 25] 1 = c l ear p o rt 25 c o rres p on d i ng c o unt er s 1? b 0 bit[2 6 ] access (busy) b it 1 ? b0 b i t [ 0] ADM6926 function description 3.3.16 read counter control & status r e gister read counter control r e gister (offset: 15h), read counter status register (offset: 16h) 1. read counter control r e gister confi g ur ation descripti o n def a ult b i t [ 8] access ( busy ) bi t 1? h 0 b i t [ 7: 0] c o u n t e r i nde x 8? h 0 2. read counter status register confi g ur ation descripti o n def a ult b i t [ 31: 0] the c o r r es po n d i n g c o u n t e r i n dex by t h e b i t [ 7: 0] i s ret u r n e d he re. 32 ? h0 3. note: this register provides user to read counter if he wants to use fast m a nage m e nt clock (fast than 5m hz). 4. rules: step 1: read the busy bit to check if the read counter m odule is busy. step 2: if the m odule is free, write th e counter index and access bit into the control register. step 3: poll the busy bit. if busy = 1? b1, wait. if busy = 1?b0, read the status register. 5. exa m ple: users want to read port 1 receive packet count step 1: read bit[8] to check if the read counter module is busy step 2: if bit[8] = 0, then write bit[8] = 1?b1, bit[7:0] = 8?b1 into the register. step 3: then port 1 receive packet c ount will be loaded in to the counter status register (offset: 16h) step 4: read counter status register (offset: 16h) and th e content read is the port 1 receive p acket count. 3.3.17 reload mdio register (offset: 17h) admtek inc. 3-57 confi g ur ation descripti o n def a ult bit[0 ] port 0 mdio reg i ster relo ad 1 = s t atu s o f po rt 0 phy attach ed w ill b e relo ad ed an d updated to t h e sw itch . after phy is relo ad ed , bit[0 ] will be cleared. 1? b 0 b i t [ 1] po rt 1 m d io r e gi st er r e l o a d 1? b 0 b i t [ 2] po rt 2 m d io r e gi st er r e l o a d 1? b 0 b i t [ 3] po rt 3 m d io r e gi st er r e l o a d 1? b 0 b i t [ 4] po rt 4 m d io r e gi st er r e l o a d 1? b 0 b i t [ 5] po rt 5 m d io r e gi st er r e l o a d 1? b 0 b i t [ 6] po rt 6 m d io r e gi st er r e l o a d 1? b 0 b i t [ 7] po rt 7 m d io r e gi st er r e l o a d 1? b 0 b i t [ 8] po rt 8 m d io r e gi st er r e l o a d 1? b 0 b i t [ 9] po rt 9 m d io r e gi st er r e l o a d 1? b 0 b i t [ 10] po rt 1 0 m d i o r e gi st er r e l o a d 1? b 0 bit[1 1 ] port 1 1 m d io reg i ster relo ad 1 ? b0 b i t [ 12] po rt 1 2 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 13] po rt 1 3 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 14] po rt 1 4 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 15] po rt 1 5 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 16] po rt 1 6 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 17] po rt 1 7 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 18] po rt 1 8 m d i o r e gi st er r e l o a d 1? b 0 ADM6926 function description confi g ur ation descripti o n def a ult b i t [ 19] po rt 1 9 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 20] po rt 2 0 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 21] po rt 2 1 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 22] po rt 2 2 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 23] po rt 2 3 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 24] po rt 2 4 m d i o r e gi st er r e l o a d 1? b 0 b i t [ 25] po rt 2 5 m d i o r e gi st er r e l o a d 1? b 0 3.3.18 spanning tree port sta t e 0 (offset: 18h) confi g ur ation descripti o n def a ult b i t [ 1: 0] po rt 0 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 3: 2] po rt 1 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 5: 4] po rt 2 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 7: 6] po rt 3 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 9: 8] po rt 4 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 1 1 : 10] po rt 5 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 13: 1 2 ] po rt 6 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 15: 1 4 ] po rt 7 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 17: 1 6 ] po rt 8 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 19: 1 8 ] po rt 9 s p an ni n g t r ee p o rt s t at us 2? h 0 b i t [ 21: 2 0 ] po rt 1 0 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 23: 2 2 ] po rt 1 1 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 25: 2 4 ] po rt 1 2 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 27: 2 6 ] po rt 1 3 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 29: 2 8 ] po rt 1 4 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 31: 3 0 ] po rt 1 5 spa n ni ng t r ee p o rt s t at us 2? h 0 note: the ADM6926 supports 4 port status to support spanning tree protocol 00 = forwarding state. the port acts as the norm al mode. 01 = disabled state. th e port en tity will not tr an sm it and receive any pac k ets. learn i ng is disabled in this state. 10 = learning state. th e port en tity will only tra n sm it and receive m a nagem e nt packets. all other packets are discarded. learning is enabled for all good fram es. 11 = blocking-not-listening. only the m a nage ment packets defined by the ADM6926 will be received and tran sm itted. all other p a ckets a r e dis carded by th e port en tity. learning is disabled in this sta t e. 3.3.19 spanning tree port sta t e 1 (offset: 19h) admtek inc. 3-58 confi g ur ation descripti o n def a ult b i t [ 1: 0] po rt 1 6 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 3: 2] po rt 1 7 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 5: 4] po rt 1 8 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 7: 6] po rt 1 9 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 9: 8] po rt 2 0 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 1 1 : 10] po rt 2 1 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 13: 1 2 ] po rt 2 2 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 15: 1 4 ] po rt 2 3 spa n ni ng t r ee p o rt s t at us 2? h 0 ADM6926 function description confi g ur ation descripti o n def a ult b i t [ 17: 1 6 ] po rt 2 4 spa n ni ng t r ee p o rt s t at us 2? h 0 b i t [ 19: 1 8 ] po rt 2 5 spa n ni ng t r ee p o rt s t at us 2? h 0 3.3.20 source port register (offset: 1ah ) confi g ur ation descripti o n def a ult b i t [ 4: 0] t h e so urce p o rt . t h e cpu can read th is reg i ster to g e t th e so urce po rt wh en h e receives a pac k et. 2? h 0 note: the value will be corr ect af ter the sa is tr ansm itted. 3.3.21 transmit p o rt register (offset: 1b h) confi g ur ation descripti o n def a ult b i t [ 25: 0] the dest i n at i o n po rt s t h e c p u want s t o fo r w ar d. 26 ? b0 bit[2 6 ] th e d e stin ation p o rts is m o re th an 1. 1 ? b0 b i t [ 27] 1 = the com m a nd i s val i d . 0 = the com m a nd i s not val i d . note: the value should be written before cpu transm its a packet. 3.3.22 counter register: offset hex. 0100h ~ 019b admtek inc. 3-59 the recei ve count of fset hex in de x descri pt i on of fset hex in de x d escri p t i on 0100h 0 port 0 receive packet c o unt 01 1a 1a port 0 receive p acket le ngth count 0101h 1 port 1 receive packet c o unt 01 1b 1b port 1 receive packet le ngth count 0102h 2 port 2 receive packet c o unt 01 1c 1c port 2 receive packet le ngth count 0103h 3 port 3 receive packet c o unt 01 1d 1d port 3 receive p acket le ngth count 0104h 4 port 4 receive packet c o unt 01 1e 1e port 4 receive packet le ngth count 0105h 5 port 5 receive packet c o unt 01 1f 1f port 5 receive packet le ngth count 0106h 6 port 6 receive packet c o unt 0120 20 port 6 receive packet le ngth count 0107h 7 port 7 receive packet c o unt 0121 21 port 7 receive packet le ngth count 0108h 8 port 8 receive packet c o unt 0122 22 port 8 receive packet le ngth count 0109h 9 port 9 receive packet c o unt 0123 23 port 9 receive packet le ngth count 010a h a port 10 receive packet c o unt 0124 24 port 10 receive packet lengt h c o unt 010bh b port 1 1 recei ve packet c o unt 0125 25 port 1 1 recei ve packet lengt h c o unt 010c h c port 12 receive packet c o unt 0126 26 port 12 receive packet lengt h c o unt 010dh d port 13 receive packet c o unt 0127 27 port 13 receive packet lengt h c o unt 010e h e port 14 receive packet c o unt 0128 28 port 14 receive packet lengt h c o unt 010fh f port 15 receive packet c o unt 0129 29 port 15 receive packet lengt h c o unt 01 10h 10 port 16 receive packet c o unt 012a 2a port 16 receive packet lengt h c o unt 01 1 1 h 1 1 port 17 receive packet c o unt 012b 2b port 17 receive packet lengt h c o unt 01 12h 12 port 18 receive packet c o unt 012c 2c port 18 receive packet lengt h c o unt 01 13h 13 port 19 receive packet c o unt 012d 2d port 19 receive packet lengt h c o unt 01 14h 14 port 20 receive packet c o unt 012e 2e port 20 receive packet lengt h c o unt 01 15h 15 port 21 receive packet c o unt 012f 2f port 21 receive packet lengt h c o unt 01 16h 16 port 22 receive packet c o unt 0130 30 port 22 receive packet lengt h c o unt 01 17h 17 port 23 receive packet c o unt 0131 31 port 23 receive packet lengt h c o unt 01 18h 18 port 24 receive packet c o unt 0132 32 port 24 receive packet lengt h c o unt 01 19h 19 port 25 receive packet c o unt 0133 33 port 25 receive packet lengt h c o unt the t r ansmit count of fset hex in de x descri pt i on of fset hex in de x d escri p t i on 0 134 3 4 por t 0 t r an sm i t pack et c o un t 0 1 4 e 4 e por t 0 t r an sm i t pack et leng th c o un t ADM6926 function description 0 135 3 5 por t 1 t r an sm i t pack et c o un t 0 14f 4 f por t 1 t r an sm i t pack et leng th c o un t 0 136 3 6 por t 2 t r an sm i t pack et c o un t 0 150 5 0 por t 2 t r an sm i t pack et leng th c o un t 0 137 3 7 por t 3 t r an sm i t pack et c o un t 0 151 5 1 por t 3 t r an sm i t pack et leng th c o un t 0 138 3 8 por t 4 t r an sm i t pack et c o un t 0 152 5 2 por t 4 t r an sm i t pack et leng th c o un t 0 139 3 9 por t 5 t r an sm i t pack et c o un t 0 153 5 3 por t 5 t r an sm i t pack et leng th c o un t 0 1 3 a 3 a por t 6 t r an sm i t pack et c o un t 0 154 5 4 por t 6 t r an sm i t pack et leng th c o un t 0 13b 3 b por t 7 t r an sm i t pack et c o un t 0 155 5 5 por t 7 t r an sm i t pack et leng th c o un t 0 1 3 c 3 c por t 8 t r an sm i t pack et c o un t 0 156 5 6 por t 8 t r an sm i t pack et leng th c o un t 0 13d 3 d por t 9 t r an sm i t pack et c o un t 0 157 5 7 por t 9 t r an sm i t pack et leng th c o un t 01 3e 3e po rt 1 0 t r an s m i t packet c o unt 01 5 8 58 po rt 1 0 t r an s m i t packet len g t h c o unt 0 13f 3 f por t 1 1 t r an smit pack et count 0 159 5 9 por t 1 1 t r an smit pack et len g t h c o un t 01 4 0 40 po rt 1 2 t r an s m i t packet c o unt 01 5a 5a po rt 1 2 t r an s m i t packet len g t h c o unt 01 4 1 41 po rt 1 3 t r an s m i t packet c o unt 01 5 b 5b port 13 t r ans m it packet length c o unt 01 4 2 42 po rt 1 4 t r an s m i t packet c o unt 01 5c 5c po rt 1 4 t r an s m i t packet len g t h c o unt 01 4 3 43 po rt 1 5 t r an s m i t packet c o unt 01 5 d 5d port 15 t r ans m it packet length c o unt 01 4 4 44 po rt 1 6 t r an s m i t packet c o unt 01 5e 5e po rt 1 6 t r an s m i t packet len g t h c o unt 01 4 5 45 po rt 1 7 t r an s m i t packet c o unt 01 5 f 5f port 17 t r ans m it packet length c o unt 01 4 6 46 po rt 1 8 t r an s m i t packet c o unt 01 6 0 60 port 18 t r ans m it packet length c o unt 01 4 7 47 po rt 1 9 t r an s m i t packet c o unt 01 6 1 61 port 19 t r ans m it packet length c o unt 01 4 8 48 po rt 2 0 t r an s m i t packet c o unt 01 6 2 62 port 20 t r ans m it packet length c o unt 01 4 9 49 po rt 2 1 t r an s m i t packet c o unt 01 6 3 63 port 21 t r ans m it packet length c o unt 01 4a 4a po rt 2 2 t r an s m i t packet c o unt 01 6 4 64 po rt 2 2 t r an s m i t packet len g t h c o unt 0 14b 4 b por t 23 t r ansmit pack et cou n t 0 165 65 port 23 t r ans m it packet length c o unt 01 4c 4c po rt 2 4 t r an s m i t packet c o unt 01 6 6 66 po rt 2 4 t r an s m i t packet len g t h c o unt 0 14d 4 d por t 25 t r ansmit pack et cou n t 0 167 67 port 25 t r ans m it packet length c o unt err o r a n d co l lisio n co unt of fset hex in de x descri pt i on of fset hex in de x d escri p t i on 0168 68 port 0 receive error coun t 0182 82 port 0 collision c o unt 0169 69 port 1 receive error coun t 0183 83 port 1 collision c o unt 016a 6a port 2 receive error c ount 0184 84 port 2 collision c o unt 016b 6b port 3 receive error c ount 0185 85 port 3 collision c o unt 016c 6c port 4 receive error c ount 0186 86 port 4 collision c o unt 6d port 5 receive error c ount 0187 87 port 5 collision c o unt 016e 6e port 6 receive error c ount 0188 88 port 6 collision c o unt 016f 6f port 7 receive error c ount 0189 89 port 7 collision c o unt 0170 70 port 8 receive error coun t 018a 8a port 8 collision c o unt 0171 71 port 9 receive error coun t 018b 8b port 9 collision c o unt 0172 72 port 10 receive error c o un t 018c 8c port 10 c o llision count 0173 73 port 1 1 recei ve error c o un t 018d 8d port 1 1 c o llision count 0174 74 port 12 receive error c o un t 018e 8e port 12 c o llision count 0175 75 port 13 receive error c o un t 0 1 8 f 8 f port 13 c o llision count 0176 76 port 14 receive error c o un t 0190 90 port 14 c o llision count 0177 77 port 15 receive error c o un t 0191 91 port 15 c o llision count 0178 78 port 16 receive error c o un t 0192 92 port 16 c o llision count 0179 79 port 17 receive error c o un t 0193 93 port 17 c o llision count 017a 7a port 18 recei ve error c o unt 0194 93 port 18 c o llision count 017b 7b port 19 receive error c o u n t 0 1 9 5 9 5 port 19 c o llision count 017c 7c port 20 recei ve error c o unt 0196 96 port 20 c o llision count 017d 7d port 21 receive error c o u n t 0 1 9 7 9 7 port 21 c o llision count 017e 7e port 22 recei ve error c o unt 0198 98 port 22 c o llision count 017f 7f port 23 receive error c o u n t 0 1 9 9 9 9 port 23 c o llision count 0180 80 port 24 receive error c o un t 019a 9a port 24 c o llision count 0181 81 port 25 receive error c o un t 0 1 9 b 9 b port 25 c o llision count 016d admtek inc. 3-60 ADM6926 electrical specification chapter 4 electrical specification 4.1 dc charac teriz a tion 4.1.1 absolute maximum rating symbol parameter rating units vc c o 3. 3v p o we r su ppl y 3. 0 t o 3 . 6 v vc c i k 1. 8v p o we r su ppl y 1. 71 t o 1. 8 9 v v in inpu t vo ltag e -0.3 to v cc33 + 0. 3 v out put v o ltag e -0 .3 to vcc 33 + 0. 3 v t s tg st ora g e tem p erat ure -5 5 t o 15 5 c p d p o we r dissipation 1. 0 w e s d esd rating 3000 v vo ut t a b l e 4-4-1 electric a l a b so l u te maximu m ratin g 4.1.2 recommen d ed operating conditions symbol typical max units vcc po wer s u p p l y 3. 13 5 3. 3 3. 46 5 v vi n in p u t v o l t a ge 0 - vcc v tj ju nct i o n o p era t i ng tem p erat u r e 0 25 11 5 c parameter min ta ble 4 - 4 - 2 rec o mme nde d ope r a t ing co nditi ons 4.1.3 dc electrical characterist ics for 3.3v operation ( under vcc=3.0v~3.6v, tj= 0 c ~ 11 5 c ) symbol parameter conditions min typical max units vil input low voltage ttl 0.8 v vih input hi gh vol t age ttl 2.0 v vol out put low voltage ttl 0.4 v out put high voltage ttl 2.3 v ri i npu t pu ll_ up / d own resistance v i l= 0v or vi h = vcc 5 0 k ? voh t a b l e 4-4-3 d c electrical c h ar act eristics fo r 3.3v op eratio n admtek inc. 4-1 ADM6926 electrical specification 4.2 ac charac teriz a tion 4.2.1 xi/osci (crystal/oscilla tor) timing figure 4-1 crystal/oscillator timin g symbol parameter conditions min typical max units t_ xi_per xi/ o sc i c l oc k pe ri o d 2 0 . 0 + 5 0pp m 20.0 - 5 0pp m 2 0 . 0 ns t_xi_hi xi/ o sc i c l oc k hi g h 8 1 0 . 0 ns t_xi_l o xi/ o sc i c l oc k l o w 8 1 0 . 0 ns t_xi_ris e xi/ o sc i c l oc k r i se ti m e , v il (m ax) to v ih (min ) 2 n s t_ xi _f all xi/ o sc i c l oc k fal l ti m e , v (m in) to v ax) ih il (m 2 n s table 4-4 crystal/oscillator timin g 4.2.1 pow er on reset 0us 50m s 100m s 150m s rs t * a l l con f i gurat i on p i n s tc o n f tr st tr st f i g u r e 4-2 pow e r on reset timin g admtek inc. 4-2 t xi ri s t xi f a l v ih x i t xi h t xi l tx i p e v il x i ADM6926 electrical specification symbol parameter conditions min max units t rs t r s t l o w peri od 15 0 m s t conf st art o f c o n f i g urat i o n pi ns 10 0 ns typical t a b l e 4-5 po w e r o n reset timin g 4.2.2 eeprom i n terface timing 0us 6. 4us 12. 8us 19. 2us eec s ee sk eed o eed i t e rdh t e rds te w d d te sk te sk te skl te skl te skh te skh ttx o d tc k tc kl tc kl tc kh tc k tc kh figure 4-3 eeprom interface timing symbol parameter conditions min typical max units t esk e e s k pe ri o d 3. 2 u s t eskl eesk lo w per i od 1 . 6 us t eskh eesk hi gh pe ri o d 1. 6 us t erds eedi to ees k rising setup tim e 10 ns t erdh eedi to ees k rising hold t i m e 10 ns t ew dd eesk fallin g to eedo ou tpu t delay tim e 2 0 n s table 4-6 eeprom interface timing 4.2.3 10base-tx mii output timing 0ns 500ns 1000ns 1500ns 2000ns 2500n s mi i _ t x c l k mi i _ t x e n mi i _ t x d admtek inc. 4-3 f i g u r e 4-4 10base-t x mii ou tp u t t i ming ADM6926 electrical specification symbol parameter conditions min typical max units t c k m i i _ txc l k peri o d 40 0 ns tckl m i i _ txcl k lo w pe rio d 16 0 240 ns tck h m i i _ txcl k hig h pe rio d 16 0 240 ns tt xo d m i i _ tx d, m i i_t x e n t o m i i _ txc l k r i si ng out put del a y 1 0 20 ns t a b l e 4-7 10b ase-t x mii outp u t timin g 4.2.4 10base-tx mii input timing 0ns 1000n s 2000n s m ii_r x clk m ii_r x dv m ii_r x d m ii_crs trx h trx s tck tckltckl tckh tck tckh figure 4-5 10base-tx mii input timing symbol parameter conditions min typical max units t c k m i i _ r x c l k peri o d 40 0 ns tckl m i i _ rxcl k lo w pe rio d 16 0 240 ns tckh mii_ rxclk high period 1 6 0 240 ns trx s mii _ crs, m i i _ rx d v a n d mii_ rxd to mii_ rxclk risin g set up 1 0 ns mii _ crs, m i i _ rx d v a n d mii_ rxd to mii_ rxclk risin g hol d 1 0 ns trx h admtek inc. 4-4 t a b l e 4-8 10b ase-t x mii in pu t t i min g ADM6926 electrical specification 4.2.5 100base-tx mii output timing 0ns 50ns 100ns 150ns 200ns 250ns mi i _ t x c l k mi i _ t x e n mi i _ t x d ttx o d tc k tc kl tc kl tc kh tc k tc kh trx h trx s tck tckltckl tckh tck tckh f i g u r e 4-6 100 base-t x mii ou tp u t t i ming symbol parameter conditions min typical max units t c k m i i _ txc l k peri o d 40 ns tckl m i i _ txcl k lo w pe rio d 16 24 ns tck h m i i _ txcl k hig h pe rio d 16 24 ns tt xo d m i i _ tx d, m i i_t x e n t o m i i _ txc l k r i si ng out put del a y 1 0 20 ns t a b l e 4-9 100 base-t x mii ou tp u t t i ming 4.2.6 100base-tx mii input timing 0ns 100n s 200n s m ii_r x clk m ii_r x dv m ii_r x d m ii_crs figure 4-7 100base-tx mii input timing symbol parameter conditions min typical max t c k m i i _ r x c l k peri o d 40 ns tckl m i i _ rxcl k lo w pe rio d 16 24 ns tckh mii_ rxclk high period 1 6 24 ns trx s mii _ crs, m i i _ rx d v a n d mii_ rxd to mii_ rxclk risin g set up 1 0 ns trx h mii _ crs, m i i _ rx d v a n d 10 ns units admtek inc. 4-5 ADM6926 electrical specification symbol parameter conditions min typical max units mii_ rxd to mii_ rxclk risin g hol d ta ble 4 - 1 1 0 0 b a s e - tx mii i nput timin g 0 4.2.7 reduced mii timing 0n s 50ns 100ns re f c l k rm i i _ t x e n t x d [ 1: 0] tt x h tt x s tc k tc k l tc k l tc k h tc k tc k h tr x h tr x s tc k tc kl tc kl tc kh tc k tc kh figure 4 - 8 re duc e d mii tim i ng (1 of 2 ) 0ns 50ns 100ns re f c lk rm i i _ crs dv r x d[ 1: 0] figure 4 - 9 re duc e d mii tim i ng (2 of 2 ) symbol conditions min typical units tck rm ii_re fcl k pe rio d 20 ns tckl rm ii_re fcl k l o w pe rio d 10 ns tck h rm ii_re fcl k hig h pe rio d 10 ns txe n , tx d t o refcl k rising setu p ti m e ns tt xh txe n , tx d t o refcl k rising hol d t i m e 2 ns trxs csrd v, rx d to refclk r i sin g setu p ti m e 4 ns trx h crsdv , r x d to refcl k ri sing hol d t i m e 2 ns parameter max tt xs 4 admtek inc. 4-6 ta ble 4 - 1 reduc e d mii tim i ng 1 ADM6926 electrical specification 4.2.8 ss_smii transmit timing 0ns 20ns 4 0ns cl k _ t x s y nc_ t x st x d [ 7 : 0 ] tc k tc k l to d tc k h tc k tc k h tt r n tc k tc k l td s tc k h tc k tc k h td h f i g u r e 4-10 ss_smii t r an smit t i ming symbol parameter conditions min typical max units t c k ss_ sm i i out p ut c l oc k pe ri o d 8 ns t c kl ss_ sm i i out p ut c l oc k l o w period 4 ns t c k h r ss _sm i i ou t put c l oc k hi g h period 4 ns tod txd a ta/tx s ync ou tpu t d e lay to clk_tx 2 5 ns ttrn txd a ta/rx s ync rise/fall time 1 ns t a b l e 4-12 ss_smii t r an smit t i ming 4.2.9 ss_smii receive timing 0ns 20ns 4 0ns cl k _ r x s y nc_ rx s r x d [7 :0 ] f i g u r e 4-11 ss_smii recei v e t i min g symbol conditions min typical max units t c k ss_ sm i i c l k _ r x c l ock pe r i od 8 ns tckl ss_smii cl k_rx low peri od 4 ns ss_smii cl k_rx hi gh peri od ns t d s r xdat a / r xsy n c set u p t o c l k _ r x 1. 5 ns parameter tckh 4 admtek inc. 4-7 ADM6926 electrical specification symbol parameter conditions min typical max units ri si ng ed ge tdh rx d a ta/rx s y n c ho ld fro m c l k_r x ri si n g e dge 1 ns t a b l e 4-13 ss_smii recei v e t i ming 4.2.10 serial man agement in terface (mdc/mdio) timing 0ns 1m s 2m s md c m d i o ( out pu t ) m d i o ( i nput ) tc k tc k l td s tc k h tc k tc k h td h to d f i g u r e 4-12 serial man a g e men t in terfac e (mdc/mdio) t i ming symbol parameter conditions min typical max units t c k ss_ sm i i c l k _ r x c l ock pe r i od 40 0 ns t c k l s s _ s m i i cl k_rx lo w peri od 20 0 ns t c kh ss_ sm i i c l k _ r x hi gh peri od 20 0 ns tod m d c to m d i o out put dela y 20 ns tds md io i npu t to md c set u p ti m e 1 0 ns tdh mdio inpu t to mdc ho l d ti me 1 0 ns admtek inc. 4-8 t a b l e 4-14 ser i al man a g e me n t in terface (mdc/mdio) t i min g ADM6926 packaging chapter 5 packaging admtek inc. 5-1 18.5 mm 20.0 +/- 0.1 mm 23.2 +/- 0.2 mm 3.4 mm max 12.5 mm 14.0 +/- 0.1 mm 17.2 +/- 0.2 mm 0.5 mm |
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